Semiconductor Symbol Pattern Width Control for CMP Defect Prevention
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Solution Overview
Problem
The miniaturization of semiconductor device patterns creates issues when symbol patterns, used for identification, have different sizes and shapes than device patterns, leading to adverse effects during processes like exposure, etching, and chemical mechanical polishing (CMP), resulting in defects such as depression formation and pattern recognition degradation.
Innovation Solution
Forming symbol patterns as isolated element patterns, either linear or dot patterns, with widths within a specific range (0.8 to 1.2 times the pattern width range on the design rule) to match the precision of device patterns, ensuring they are formed in the same layer and processed uniformly with device patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If symbol patterns are formed with wider line widths for better visibility, then identification precision is improved, but manufacturing precision deteriorates due to process optimization being skewed toward device pattern dimensions
Solution Approach 1:
The patent changes the dimensional parameters of symbol patterns to match device pattern specifications. Symbol patterns are designed with line widths and shapes identical to device patterns in the same layer, transforming them from visually-optimized wide features to manufacturing-optimized features that conform to process capabilities. This parameter alignment ensures both patterns are formed with the same precision during exposure, etching, and CMP processes.
Solution Approach 2:
The patent applies different design rules to different pattern types within the same layer. Device patterns follow standard design rules optimized for electrical performance, while symbol patterns are assigned matching design rules that replicate device pattern dimensions. This local quality differentiation ensures symbol patterns receive the same manufacturing precision treatment as device patterns without compromising their identification function.
2Adaptability or versatility
If symbol patterns contain complex design elements (T-shape, cross-shape) for identification, then identification capability is improved, but manufacturing precision deteriorates due to process conditions being optimized only for rectangular device patterns
Solution Approach 1:
The patent segments complex symbol patterns into basic geometric elements (rectangles, squares, lines) that match device pattern components. By constructing symbols from these standardized shapes rather than using complex T-shapes or crosses, the patterns conform to process-optimized geometries. This segmentation allows symbol patterns to maintain identification capability while achieving manufacturing precision equivalent to device patterns.
Solution Approach 2:
The patent changes the geometric parameters of symbol patterns to exclude complex shapes like T-characters and crosses. Instead, symbols are formed using only rectangular and square elements with dimensions matching device patterns. This parameter restriction ensures all patterns are formed under identical process conditions optimized for simple geometries, eliminating manufacturing precision deterioration.
3Measurement precision
If symbol patterns are formed with larger sizes for visibility, then identification precision is improved, but reliability deteriorates due to adverse effects during exposure, etching, and CMP processes
Solution Approach 1:
The patent changes the size parameters of symbol patterns to match device pattern dimensions. By making symbol patterns the same size as device patterns in the same layer, they undergo exposure, etching, and CMP processes under identical conditions. This parameter alignment eliminates the adverse effects that occur when larger symbol patterns are processed with conditions optimized for smaller device patterns, thereby improving process reliability.
Solution Approach 2:
The patent makes symbol patterns universal with device patterns by assigning them identical dimensional characteristics. Both pattern types share the same line widths, shapes, and size ranges, allowing a single set of process conditions to reliably form both device and symbol patterns. This universality eliminates the need for separate process optimization, improving overall process reliability.
4Illumination intensity
If symbol patterns use different line widths than device patterns, then visibility is improved, but manufacturing precision deteriorates due to non-uniform process application
Solution Approach 1:
The patent changes the line width parameter of symbol patterns to match device pattern line widths. By eliminating line width differentiation between symbol and device patterns, both are formed with the same precision during lithography and subsequent processing. This parameter unification ensures uniform application of exposure, etching, and CMP processes, eliminating manufacturing precision deterioration while maintaining sufficient visibility for identification.
Solution Approach 2:
The patent creates homogeneity between symbol patterns and device patterns by using identical line widths and geometric characteristics. This homogeneity allows a single set of process parameters to be applied uniformly across the entire wafer, ensuring consistent manufacturing precision for all patterns regardless of their functional category. The uniformity eliminates variability in line width control precision that arises from differential process optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach suppresses the generation of adverse effects caused by defective symbol pattern shapes, maintaining process integrity and improving pattern recognition precision by ensuring the symbol patterns are formed with the same precision as device patterns.
Implementation Method 1
chemical mechanical polishing (CMP)
Data Source
AI summary
A plurality of device patterns constituting part of an electronic circuit are formed over the surface of a substrate. A symbol pattern to be used for an identification sign is formed in the same layer as the device patterns. A width of the device pattern is within a pattern width range on a design rule. The symbol pattern is formed by a plurality of isolated element patterns. The element pattern is either a linear pattern or a dot pattern. A width of the element pattern is equal to or larger than 0.8 time a lower limit value of the pattern width range and equal to or smaller than 1.2 times an upper limit value of the pattern width range.