Semiconductor Terminal Layout for Ring Daisy Chain Memory Links
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Solution Overview
Problem
In memory systems with ring daisy chain interconnections, longer interconnections lead to increased power consumption and reduced communication rates.
Innovation Solution
The semiconductor device features receiving and transmitting terminals symmetrically positioned with 90-degree rotational symmetry about a center, optimizing the length and linearity of connections between communication chips, thereby minimizing power consumption and enhancing communication efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If communication chips are interconnected as a ring daisy chain, then connectivity between chips is achieved, but power consumption increases and communication rate decreases
Solution Approach 1:
The patent applies asymmetry by positioning transmitting and receiving terminals in non-symmetric locations on the substrate, specifically arranging them to minimize connection lengths in the ring daisy chain configuration. This asymmetric arrangement optimizes signal transmission paths to reduce power consumption while maintaining connectivity.
Solution Approach 2:
The patent utilizes dimensional optimization by carefully arranging terminals in two-dimensional space on the substrate surface. By optimizing the spatial distribution and positioning of transmitting and receiving terminals across different dimensions of the substrate, the connection lengths are minimized, thereby reducing power consumption in the ring daisy chain interconnection.
2Reliability
If communication chips are interconnected as a ring daisy chain, then connectivity between chips is achieved, but communication rate reduces
Solution Approach 1:
The asymmetric positioning of transmitting and receiving terminals optimizes the signal transmission paths by minimizing connection lengths. This asymmetric arrangement reduces signal degradation and transmission delays, thereby improving communication rate while maintaining ring daisy chain connectivity.
Solution Approach 2:
The patent changes the geometric parameters of terminal positioning on the substrate to optimize communication performance. By adjusting the positions, orientations, and spacing of transmitting and receiving terminals, the connection lengths and signal transmission characteristics are optimized to enhance communication rate.
3Use of energy by moving object
If terminals are arranged to minimize connection length, then power consumption reduces, but terminal positioning complexity increases
Solution Approach 1:
The patent applies local quality by optimizing terminal positioning in specific local regions of the substrate. Rather than requiring complex global optimization, the transmitting and receiving terminals are arranged in locally optimized positions that minimize connection lengths in critical areas, thereby reducing power consumption with manageable positioning complexity.
Data Source
AI summary
According to one embodiment, a semiconductor device includes receiving terminals on a surface of a substrate to receive first signals and transmitting terminals on the surface of the substrate to transmit second signals. The transmitting terminals are symmetrically positioned on the surface of the substrate with respect to the receiving terminals at a substantially 90 degree rotation about a rotation center position. The ordering of the transmitting terminals along the surface of the substrate from the rotation center position matches the ordering of the receiving terminals along the surface of the substrate from the rotation center position.