Semiconductor Device Terminal Stacking for Inductance Reduction
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing inductance in upper-lower arm circuits, which affects the efficiency of electric power conversion and current path simplification.
Innovation Solution
The semiconductor device configuration includes multiple main terminals with lateral surfaces facing each other, arranged in a specific pattern to reduce inductance, with at least three main terminals continuously arranged in one direction, and partially or entirely placed in regions extending from the semiconductor element's end surfaces, simplifying the current path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If main terminals are arranged in a conventional configuration, then the device structure is simple, but the inductance is high which reduces power conversion efficiency
Solution Approach 1:
The patent transitions from a conventional linear or scattered terminal arrangement to a three-dimensional stacked configuration where main terminals are vertically arranged above each other. This spatial reorganization in the vertical dimension reduces the current path length and loop area, thereby reducing inductance and improving power conversion efficiency while maintaining manufacturing feasibility through standardized packaging processes
2Ease of operation
If main terminals are placed far apart, then the current path is long, but the inductance increases which affects circuit performance
Solution Approach 1:
The patent utilizes vertical stacking to position main terminals directly above each other in the thickness direction of the semiconductor substrate. This three-dimensional arrangement dramatically shortens the current path length between terminals compared to planar arrangements, reducing inductance and improving circuit performance while maintaining ease of connection
3Loss of energy
If multiple main terminals are continuously arranged in one direction, then the inductance is reduced, but the device width increases
Solution Approach 1:
The patent arranges multiple main terminals in a vertical stack along the thickness direction of the semiconductor substrate rather than spreading them out in the planar direction. This vertical configuration reduces inductance by minimizing current loop area while containing the device footprint, as the terminals occupy minimal additional width compared to a linear horizontal arrangement
Data Source
AI summary
A semiconductor device configures one arm of an upper-lower arm circuit, and includes: a semiconductor element that includes a first main electrode and a second main electrode, wherein a main current between the first main electrode and the second main electrode; and multiple main terminals that include a first main terminal connected to the first main electrode and a second main terminal connected to the second main electrode. The first main terminal and the second main terminal are placed adjacent to each other; A lateral surface of the first main terminal and a lateral surface of the second main terminal face each other in one direction orthogonal to a thickness direction of the semiconductor element.