Semiconductor Test Circuit for Wafer and Package Delay Measurement
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Solution Overview
Problem
Conventional semiconductor device test circuits can only measure delay times in the wafer state and not during or after the packaging process, limiting the ability to accurately assess element delays throughout the device's lifecycle.
Innovation Solution
Incorporating a control signal generator, transmission gates, a delay circuit, and a latch that allow for the generation and measurement of test control signals, enabling the measurement of delay times both in the wafer and package states by selectively switching between normal and test operations using an external clock signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If test circuits are disposed in spaces between semiconductor devices on a wafer, then delay times can be measured in the wafer state, but the test circuits cannot be measured during or after the packaging process
Solution Approach 1:
The test circuit is merged with the semiconductor device structure by integrating it into the device itself rather than placing it separately in wafer spaces. The test circuit includes a delay circuit with multiple inverters that are part of the device architecture, allowing the same circuit to serve both as the device under test and as the measurement instrument.
Solution Approach 2:
The test circuit is designed to perform multiple functions: it can measure delay times in the wafer state during fabrication, and continue to function after packaging to measure delay times in the packaged device state. This multi-functionality is achieved by making the test circuit an integral part of the device that operates independently of the measurement environment.
2Adaptability or versatility
If conventional test circuits are used, then simple structure is maintained, but the ability to measure delay times in both wafer and package states is lost
Solution Approach 1:
The test circuit is merged with the semiconductor device structure by integrating it into the device itself rather than placing it separately in wafer spaces. The test circuit includes a delay circuit with multiple inverters that are part of the device architecture, allowing the same circuit to serve both as the device under test and as the measurement instrument.
Solution Approach 2:
A control signal generator is introduced as an intermediary component that generates test control signals to enable the delay circuit to operate in measurement mode. This intermediary allows the device to switch between normal operation and test measurement modes without requiring separate test circuits, thereby achieving multi-state measurement capability while controlling structural complexity.
Data Source
AI summary
A semiconductor device may include a control signal generator configured to generate a test control signal in response to an externally applied test command signal. First and second transmission gates may be configured to open and close together in response to a test clock signal pulse and the test control signal. A delay circuit may be coupled between the first and second transmission gates so that the delay circuit is configured to receive a test input signal through the first transmission gate and to transmit a delayed test input signal to the second transmission gate, and the delayed test input signal may correspond to the test input signal. A latch may be coupled between the second transmission gate and an output of the semiconductor device, and the latch may be configured to latch a first logic value when a duration of the test clock signal pulse is less than a delay of the delay circuit and to latch a second logic value when a duration of the test clock signal pulse is greater than the delay of the delay circuit, and the first and second logic values be different. Related methods are also discussed.