Semiconductor Test Correlation for Wafer-to-Package Variation Detection
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Solution Overview
Problem
The increasing complexity of semiconductor processes leads to variations in semiconductor devices, necessitating efficient and accurate testing methods to identify factors affecting device quality, which current testing methods are time-consuming and costly.
Innovation Solution
A method and system for testing semiconductor devices by correlating data from wafer and package tests to identify key factors influencing variation, allowing for targeted quality control and efficient manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If total semiconductor devices are tested to detect variations, then reliability is improved, but loss of time and cost increase
Solution Approach 1:
The patent segments the testing process into two stages: wafer-level testing (first data) and package-level testing (second data). By dividing the total testing into hierarchical levels and analyzing correlations between them, the system identifies critical factors early at the wafer stage, reducing the need for exhaustive package-level testing while maintaining detection accuracy.
Solution Approach 2:
The patent performs preliminary testing and data collection at the wafer level before packaging. By obtaining first data from wafer testing and correlating it with second data from package testing, the system identifies affecting factors in advance, enabling early quality control decisions and reducing subsequent testing requirements.
2Reliability
If total semiconductor devices are tested to detect variations, then reliability is improved, but cost increases
Solution Approach 1:
The patent segments testing into wafer-level and package-level stages, allowing cost-effective early detection at the wafer stage. By analyzing correlations between first data (wafer) and second data (package), the system identifies critical factors early, reducing expensive package-level testing while maintaining reliability.
Solution Approach 2:
The patent extracts and analyzes correlation information from the relationship between wafer-level and package-level test data. By taking out the correlation analysis as a separate function, the system identifies affecting factors early in the process, enabling targeted quality control that reduces overall testing costs while maintaining detection accuracy.
3Adaptability or versatility
If complexity of semiconductor process increases with degree of integration, then functionality is improved, but difficulty of detecting and measuring increases
Solution Approach 1:
The patent extracts correlation information from the complex relationship between wafer-level and package-level test data. By separating the correlation analysis function, the system simplifies the detection process for complex integrated devices, identifying affecting factors without being overwhelmed by process complexity.
Solution Approach 2:
The patent introduces correlation analysis as an intermediary mechanism that bridges wafer-level and package-level testing. This intermediary function simplifies the detection of variations in complex integrated devices by translating complex process variations into identifiable affecting factors through statistical correlation.
Data Source
AI summary
A method of testing a semiconductor device includes obtaining first data generated by testing wafers, each including a plurality of chips, the obtaining based on a plurality of first items, obtaining second data generated by testing packages, each including a packaged chip, the obtaining based on a plurality of second items, detecting correlations between the plurality of first items and the plurality of second items, based on the first data and the second data, identifying at least one first item affecting variation of the packages, based on the correlations, and testing the identified at least one first item.