Semiconductor Test Structure for Flipped Gate NMOS Monitoring
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Solution Overview
Problem
There is a lack of a suitable test key structure for monitoring the electrical performance of flipped gate N-type metal-oxide-semiconductor field effect transistors (NMOS FETs) in semiconductor wafer acceptance tests, as conventional test structures do not resemble the flipped gate NMOS FETs found in die areas.
Innovation Solution
A semiconductor structure with a test structure disposed in the scribe line area, comprising a flipped gate NMOS FET and an NMOS FET test device, both with the same conductivity type channels and opposite conductivity type gate electrodes, allowing for individual measurement and ensuring the same fabrication processes as the devices in the die areas, with electrical connections to test pads for monitoring the threshold voltage difference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test structures are used, then the test structure is simple and easy to manufacture, but the test structure cannot effectively monitor the electrical performance of flipped gate NMOS FETs
Solution Approach 1:
The patent creates test structures that are copies of the actual flipped gate NMOS FET devices found in the die areas. The test structure includes a first flipped gate NMOS FET and a second NMOS FET with identical fabrication processes, channel conductivity types, and structural characteristics. This copying approach allows the test structure to accurately monitor the electrical performance and threshold voltage differences of the production devices without requiring complex external measurement systems.
Solution Approach 2:
The test structure serves multiple functions: it monitors threshold voltage differences, detects electrical performance variations, and validates fabrication process consistency. By integrating both flipped gate and conventional NMOS FETs in the same test structure with opposite conductivity type gate electrodes, the system can simultaneously test different device configurations and provide comprehensive quality assurance for bandgap reference circuits.
2Productivity
If traditional monitoring methods are used, then the measurement process is simple, but the cycle time is about two months
Solution Approach 1:
The test structure is fabricated simultaneously with the production devices in the same wafer and undergoes the same fabrication processes. This preliminary action allows electrical performance monitoring to begin much earlier in the manufacturing cycle, reducing the overall cycle time from two months to a fraction of that time while maintaining measurement precision through direct comparison of threshold voltages between flipped gate and conventional NMOS FETs.
Solution Approach 2:
The test structure provides immediate feedback on fabrication process variations by measuring the threshold voltage difference between the flipped gate NMOS FET and the conventional NMOS FET. This feedback mechanism enables real-time process monitoring and adjustment, significantly reducing the cycle time required to validate device performance while maintaining high measurement precision through direct electrical characterization.
3Reliability
If the test structure uses different conductivity types for both devices, then the fabrication process is simpler, but it cannot detect the reference voltage of bandgap reference circuits
Solution Approach 1:
The test structure employs local quality variation by using opposite conductivity types for the gate electrodes of the flipped gate NMOS FET and the conventional NMOS FET, while keeping the channel conductivity types the same. This local differentiation in gate electrode conductivity allows the structure to detect reference voltage characteristics essential for bandgap reference circuits, while the overall fabrication process remains consistent with standard semiconductor manufacturing techniques.
Data Source
AI summary
A semiconductor structure is provided. The semiconductor structure includes a semiconductor wafer and a test structure. The semiconductor wafer has a substrate having a scribe line area and die areas. The die areas are separated by the scribe line area. The test structure is disposed in the scribe line area. The test structure includes an isolation feature, a first transistor test device, a second transistor test device. The isolation feature is located in the substrate. The first transistor test device and the second transistor test device are disposed on opposite sides of the isolation feature. Channels of the first transistor test device and the second transistor test device have the same conductivity type. A first gate electrode of the first transistor test device and a second gate electrode of the second transistor test device have opposite conductivity types.