Semiconductor Test Interface Pin Reduction via Signal Merging
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Solution Overview
Problem
Conventional semiconductor devices with JTAG modules have a high number of additional pins, which is inefficient, and the functionality of pins used as JTAG test pins in test mode cannot be effectively tested, posing a challenge in reducing pin count while maintaining testing capabilities.
Innovation Solution
A semiconductor device design where a work cycle signal is used simultaneously as a test data clock signal, reducing the number of pins needed by omitting the separate data clock signal line, and utilizing a multiplexer or switch to switch pin functions based on operating mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate test data clock signal line is provided in addition to work cycle signal lines, then testing capability is improved, but the number of pins increases
Solution Approach 1:
The patent combines the test data clock signal function with the work cycle signal line by providing a clock signal generator that outputs the test data clock signal on an existing work cycle signal line. This merging eliminates the need for a separate dedicated clock line while maintaining full testing capability, directly resolving the contradiction between testing capability and pin count.
Solution Approach 2:
The work cycle signal line is designed to serve dual purposes: it functions as a normal work cycle signal line during device operation and as a test data clock signal line during testing. The clock signal generator enables this multi-functionality by dynamically providing the appropriate signal type on the same physical line, thereby reducing the total number of pins required.
2Quantity of substance
If pins are multiplexed between JTAG test mode and normal operation mode, then the number of pins is reduced, but the functionality of the pin in normal mode cannot be effectively tested
Solution Approach 1:
The patent introduces a clock signal generator as an intermediary component that enables the work cycle signal line to function as a test data clock signal line. This intermediary provides the necessary clock signal during testing without interfering with the normal operation of the line, allowing both testing and normal functionality to be preserved and tested effectively.
Data Source
AI summary
A semiconductor device with test interface, as well as to a method for operating a semiconductor device is disclosed. In one embodiment, in a test operating mode, the semiconductor device is, via a first pin, supplied with a work cycle signal synchronized with a test environment and, via at least one second pin, with test data. In accordance with a first embodiment it is suggested, so as to reduce the number of pins, that the work cycle signal is simultaneously used as test data clock signal.