Semiconductor Test Membrane With Aperture Patterns for Micro-Bumps
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Solution Overview
Problem
Existing semiconductor test methods face challenges in accurately testing electrical connections of micro bumps in stacked semiconductor devices without causing damage or misalignment, particularly due to the small size and susceptibility of these bumps to deformation.
Innovation Solution
A semiconductor test device with a membrane portion featuring aperture patterns and conductive thin film layers, along with a holder portion, is designed to make precise electrical contact with micro bumps while minimizing damage, using materials with low thermal expansion and elasticity to accommodate fine pitches and widths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional test methods are used to contact micro bumps, then testing can be performed, but damage to micro bumps occurs due to their small size and susceptibility to deformation
Solution Approach 1:
The patent employs a flexible membrane structure with aperture patterns that can elastically deform to accommodate micro bumps without causing damage. The thin film membrane allows gentle contact while maintaining testing functionality, resolving the contradiction between achieving reliable electrical contact and preventing damage to fragile micro bumps.
Solution Approach 2:
The membrane structure is designed with inherent elasticity and compliance to cushion the contact force before actual electrical testing occurs. This pre-cushioning effect protects micro bumps from excessive stress while enabling subsequent reliable measurement of electrical connections.
2Measurement precision
If precise alignment is required for testing micro bumps, then measurement accuracy improves, but alignment errors occur due to the fine pitch and small dimensions
Solution Approach 1:
The membrane is divided into multiple aperture patterns that correspond to individual micro bump locations. This segmentation allows each aperture to be independently aligned with its target micro bump, improving overall alignment precision while accommodating the fine pitch through distributed positioning features.
Solution Approach 2:
The patent introduces alignment features that extend beyond the simple planar contact dimension, using vertical aperture patterns and multi-layer structural alignment markers to achieve precise positioning in three-dimensional space, thereby improving alignment accuracy for fine-pitch micro bumps.
Data Source
AI summary
The present invention relates to a manufacturing method of a semiconductor test device. A semiconductor test device according to an embodiment of the present invention, which is a semiconductor test device for testing an electrical connection of a semiconductor, may include: a first membrane portion comprising a first surface and a second surface opposite to the first surface and including a plurality of first aperture patterns extending from the first surface toward a direction of the second surface; and a second membrane portion comprising a third surface, connected to the first surface of the first membrane portion, and a fourth surface opposite to the third surface and including a plurality of second aperture patterns extending from the fourth surface toward a direction of the third surface.