Semiconductor Test Pad Segmentation for Probing and Signal Integrity
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Solution Overview
Problem
The challenge in semiconductor devices is the difficulty in probing small pads during wafer testing due to the significant size decrease in micro-bump technology, which limits the ability to increase the number of input/output pins required for higher bandwidth operations, especially in mobile memory devices.
Innovation Solution
The implementation of larger test pads with a pad connection unit that electrically couples these pads to the integrated circuit during a test mode, allowing for sufficient electrical contact with testing probes, and disconnects them during normal operating modes to reduce capacitance and maintain efficient signal transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If micro-bump technology is used to decrease pad size, then the number of IO pins can be increased for higher bandwidth, but probing during wafer testing becomes difficult
Solution Approach 1:
The invention divides pads into two distinct types: small bump pads for normal operation and large test pads for wafer testing. This segmentation allows each pad type to be optimized for its specific function, resolving the contradiction between having many small pads and being able to probe them effectively.
Solution Approach 2:
Different regions of the semiconductor device have different pad characteristics. The test pads are specifically designed with larger dimensions in certain locations to facilitate probing, while bump pads maintain smaller dimensions for high-density I/O. This local differentiation resolves the probing difficulty without sacrificing the high bandwidth capability.
2Difficulty of detecting and measuring
If test pads are made larger for easier probing, then wafer testing becomes feasible, but device area is consumed
Solution Approach 1:
By segmenting the pad structure into test-specific and operation-specific pads, the invention allows large pads to exist only where needed for testing, rather than making all pads large. This minimizes the total area consumed while ensuring testability.
Solution Approach 2:
The invention applies the 'excessive action' principle by providing larger pads than strictly necessary for signal transmission, but only for test purposes. The excessive size is localized to test pads and does not affect the overall device area significantly, as these pads are not needed during normal operation.
3Difficulty of detecting and measuring
If test pads remain connected during normal operation, then probing is easy, but capacitance increases and signal transfer efficiency decreases
Solution Approach 1:
The pad connection structure is made dynamic through the pad connection unit, which can switch between connected and disconnected states. During wafer testing, the test pads are connected to facilitate probing. During normal operation, the pad connection unit disconnects the test pads to minimize capacitance and maintain signal transfer efficiency. This dynamic behavior resolves the contradiction between ease of probing and signal efficiency.
Data Source
AI summary
A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.