Semiconductor Test Structures Mask Reuse Alignment
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Solution Overview
Problem
In semiconductor processing, the reuse of masks is hindered by interference between reference marks in different layers, which complicates alignment and evaluation, and using separate masks for each layer is costly and inefficient.
Innovation Solution
A methodology and mask design that allows the same mask to be used for multiple layers by strategically shifting the mask to avoid interference between reference marks, using openings to remove marks from the resist after initial exposure, and employing test structures to assess alignment without interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a mask is reused for multiple layers, then cost and complexity are reduced, but reference marks from prior uses interfere with subsequent alignment
Solution Approach 1:
The patent extracts and removes reference marks from the resist after initial exposure using openings in the mask. This allows the same mask to be reused for subsequent layers without the reference marks interfering with alignment, as the marks are physically removed from the resist layer.
Solution Approach 2:
The patent performs preliminary removal of reference marks from the resist before subsequent mask exposures. By removing the marks in advance through selective exposure via openings, the system prepares the resist layer to receive new alignment marks from the reused mask without interference.
2Manufacturing precision
If separate masks are used for each layer, then alignment precision is maintained, but cost and process complexity increase
Solution Approach 1:
The patent makes a single mask universal for use across multiple layers by incorporating openings that enable selective removal of reference marks. The same mask can be reused for different layers without requiring separate masks for each layer, reducing mask management complexity while maintaining alignment precision through the mark removal mechanism.
3Measurement precision
If reference marks are retained on the resist, then alignment reference is available, but interference occurs with subsequent layer alignment
Solution Approach 1:
The patent extracts reference marks from the resist by using openings in the mask to selectively expose and remove the marks after initial alignment. This extraction eliminates the harmful interference effect while the marks have already served their purpose for alignment measurement in the previous layer.
Solution Approach 2:
The patent converts the potentially harmful interference of retained reference marks into a beneficial process by using the marks themselves as targets for selective removal. The openings in the mask are positioned to expose and remove the marks, transforming the interference problem into a controlled removal mechanism that enables mask reuse.
Data Source
AI summary
Different types of test structures are formed during semiconductor processing. One type of test structure comprises features that are aligned with one another and that are formed from different layers. Other types of test structures comprise features formed from respective layers that are not aligned with other test structure features. The different types of test structures are formed with a single mask that is used in a manner that also allows alignment marks to be formed which do not interfere with one another as subsequent layers are patterned. The different types of test structures can provide insight into performance characteristics of different types of devices as the semiconductor process proceeds.