Semiconductor Test System Tabular Plan Parallel Execution
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Solution Overview
Problem
Current semiconductor test systems face challenges in maintaining high throughput and ease of maintenance due to complex test plans that require advanced programming skills and are inflexible, with interpreted programs executing slower than compiled ones and being difficult to debug and understand.
Innovation Solution
A semiconductor test system with a tester controller that executes machine-executable instructions based on a user-generated tabular form test plan, incorporating asynchronous and synchronous parallel execution, and dispatch operation control to simplify program flow control and improve readability and maintainability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If interpreted programs are used for test plans, then ease of modification and maintenance is improved, but execution speed deteriorates
Solution Approach 1:
The system dynamically switches between interpreted execution mode (for ease of modification and maintenance) and compiled execution mode (for high-speed execution). The tester controller includes both an interpreter that executes test plans line-by-line and a compiler that compiles test plans to machine code, allowing the system to adapt its execution mode based on performance requirements while maintaining the benefits of both approaches.
2Adaptability or versatility
If complex test plans with advanced programming are used, then functionality and control capability are improved, but ease of understanding and debugging deteriorates
Solution Approach 1:
The test plan is segmented into multiple lines with each line representing a discrete test step or command. This line-by-line structure allows users to understand and debug the test plan sequentially, improving readability and maintainability while still enabling complex testing functionality through the accumulation of multiple simple steps.
Solution Approach 2:
The system introduces an intermediary layer (the tabular test plan format with standardized columns for command, parameter, and device information) that sits between the user's testing requirements and the complex hardware control operations. This intermediary structure simplifies the interface for users while maintaining full control capability over the testing equipment.
3Device complexity
If sequential execution of test plan lines is used, then simplicity of execution control is improved, but throughput deteriorates
Solution Approach 1:
The execution control dynamically adapts between sequential and parallel modes. The tester controller executes test plan lines sequentially when simplicity is required, but can launch multiple execution threads in parallel when throughput is prioritized, allowing the system to optimize execution control complexity versus productivity based on specific testing scenarios.
Solution Approach 2:
The system maintains continuous useful action by allowing overlapping execution of test plan lines through parallel threading. While maintaining the logical sequential structure for control simplicity, the system can execute independent test operations concurrently, ensuring that productive work continues without idle waiting periods between sequential steps.
Data Source
AI summary
A semiconductor test system includes test head pins; per-pin resources which are connectable to the test head pins on a one-to-one basis; shared resources, each of which is connectable to one of the test head pins; a tester controller for controlling the per-pin resources and the shared resources; and a tabular-form test plan including: a first column for specifying a measurement function that uses at least one of the per-pin resources and the shared resources; and at least one second column for specifying input and output parameters of the measurement function, the tabular-form test plan further including program rows, the tabular-form test plan being executed by the tester controller, the tabular-form test plan further including a third column for specifying how rows that are executed by asynchronous parallel execution are to be grouped.