Semiconductor Test Tray Vertical Mounting Orientation

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Solution Overview

Problem

Existing test trays for semiconductor devices have limitations in loading a large number of devices due to the wide footprints of semiconductor devices like DIMMs when mounted in a lying-down state, which restricts the tray size and capacity.

Innovation Solution

A test tray design featuring a frame with inserts that allow semiconductor devices with lateral terminals to be mounted at an angle, utilizing a push unit with an advance/retreat member and a pressing-direction switching unit to efficiently align and mount the devices, thereby optimizing tray capacity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If semiconductor devices are mounted in a lying-down state on the tray, then the devices can be easily loaded and positioned, but the wide footprint of each device limits the number of devices that can be loaded on the tray

Engineering Contradiction:
Improveease of loading devicesVSAvoidnumber of devices loaded on tray
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent changes the mounting orientation of semiconductor devices from a horizontal lying-down state to a vertical standing state. This dimensional change allows devices to be arranged upright on the tray, significantly reducing the horizontal footprint each device occupies and thereby increasing the total number of devices that can be loaded on the same tray area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces asymmetric mounting configurations where devices are positioned at different orientations and locations on the tray. The tray includes multiple mounting positions with varying orientations, allowing some devices to be mounted vertically while others may be positioned differently, optimizing space utilization and increasing overall device capacity beyond symmetric horizontal arrangement.

Inventive Principle:
Principle #4Asymmetry

2Area of stationary object

If the tray size is reduced to accommodate fewer devices, then the footprint per device is reduced, but the total testing capacity decreases

Engineering Contradiction:
Improvetray sizeVSAvoidtesting capacity
Core Design Contradiction:
Area of stationary objectVSProductivity

Solution Approach 1:

By transitioning from horizontal to vertical mounting, the patent effectively utilizes the vertical dimension of the tray space. This allows the same tray physical dimensions to accommodate more devices vertically stacked or upright positioned, thereby maintaining tray size while increasing testing capacity through improved spatial arrangement.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Quantity of substance

If multiple rows and columns are added to the tray to increase device capacity, then more devices can be loaded, but the tray complexity and size increase

Engineering Contradiction:
Improvenumber of devices loadedVSAvoidtray structure complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the tray into multiple independent mounting positions or sections, each capable of holding individual semiconductor devices in vertical orientations. This segmentation allows flexible arrangement of devices across different zones of the tray, enabling high device capacity through modular positioning rather than requiring a single complex continuous structure, thereby managing tray complexity through standardized modular units.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250164543A1Test tray for semiconductor devices and test apparatus using the same
Publication Date: 2025.05.22 ATECO INC
  • US20250164543A1 patent drawing
  • US20250164543A1 patent drawing
  • US20250164543A1 patent drawing

AI summary

Disclosed is a test tray to which a semiconductor device is mounted according to an embodiment of the disclosure, the test tray including: a plurality of inserts to which the semiconductor devices are mounted; and a frame which supports the inserts in arrangement respectively corresponding to sockets of a test apparatus and has a length in a first axis and a width in a second axis.