Semiconductor Integrated Circuit Test Mode Voltage Generation
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Solution Overview
Problem
The increasing number of pads required for channel allocation in DDR4 DRAM devices during test modes reduces the number of devices that can be tested simultaneously, increasing production costs and time due to the absence of a voltage booster, which necessitates external supply of both power supply voltage VDD and boosted voltage VPP.
Innovation Solution
A semiconductor integrated circuit design that includes a first pad for receiving a first voltage, a second pad for receiving a second voltage, and an internal voltage generation circuit to generate a third voltage during test mode, allowing the internal circuit to operate using both voltages in normal and test modes without allocating additional channels for the boosted voltage, thereby reducing the number of pads needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both power supply voltage VDD and boosted voltage VPP are received through external pads in test mode, then the internal circuit can perform test operations, but the number of pads increases reducing the number of devices that can be tested simultaneously
Solution Approach 1:
The first pad is designed to serve dual purposes: receiving power supply voltage VDD during normal mode and receiving boosted voltage VPP during test mode. This multi-functionality eliminates the need for a separate voltage booster pad, allowing the same physical pad to fulfill different voltage supply requirements based on operational mode, thereby increasing the number of devices that can be tested simultaneously while maintaining full test operation capability.
2Area of stationary object
If a voltage booster is included to generate boosted voltage VPP internally, then the number of external pads can be reduced, but the occupied area increases
Solution Approach 1:
The voltage booster function is extracted and removed from the chip design. Instead of including an internal voltage booster circuit that would occupy significant area, the boosted voltage VPP is supplied externally through the existing first pad during test mode. This extraction eliminates the area-consuming voltage booster component while maintaining the necessary voltage supply capability through external provision.
3Area of stationary object
If the first pad receives both power supply voltage VDD and boosted voltage VPP, then the number of pads is reduced, but the voltage level management becomes complex
Solution Approach 1:
The function of the first pad is made dynamic rather than static. The pad's received voltage type (VDD or VPP) changes based on the operational mode (normal or test). During normal mode, the first pad receives VDD; during test mode, it receives VPP. This dynamic reconfiguration allows the same pad to handle different voltage levels appropriately for each mode, reducing pad count while managing voltage complexity through mode-dependent configuration.
Data Source
AI summary
A semiconductor integrated circuit includes a first pad configured to receive a first voltage, a second pad configured to receive a second voltage, an internal voltage generation circuit configured to generate a third voltage having the same voltage level as the first voltage in response to the second voltage during a test mode, and an internal circuit configured to perform a normal operation using the first voltage and the second voltage during a normal mode and perform a test operation using the second voltage and the third voltage during the test mode.