Semiconductor Testing Signal Settling Profile Correction
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Solution Overview
Problem
Semiconductor device testing is limited by the need to wait for output signals to settle, leading to device-limited throughput and increased costs due to wasted time during settling intervals, which can account for a significant percentage of the total testing time.
Innovation Solution
A method and system that compute and subtract a settling profile from output signal samples to adjust them, allowing for analysis during the settling interval without waiting for the signal to reach steady state, thereby reducing the time required for testing and increasing throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the test system waits for output signals to reach steady state before sampling, then measurement precision is improved, but productivity deteriorates due to increased testing time
Solution Approach 1:
The system performs preliminary computation of the settling profile during the settling interval itself, rather than waiting for steady state. By calculating the profile from samples collected during settling and using it to generate adjusted samples, the system enables analysis before the signal fully settles, thereby reducing testing time while maintaining measurement accuracy through computational correction
Solution Approach 2:
The settling profile acts as an intermediary that bridges the gap between raw samples collected during settling and the desired steady-state measurements. By modeling the drift behavior and using this profile to adjust samples, the system eliminates the need to wait for natural settling while maintaining measurement precision through mathematical correction
2Productivity
If samples are collected during the settling interval, then productivity is improved by reducing wait time, but measurement precision deteriorates due to near-DC drift and spectral leakage
Solution Approach 1:
The system uses feedback from the observed settling behavior to correct the measurements. By continuously monitoring the drift during settling and using this information to update the settling profile, the system can compensate for the near-DC drift and spectral leakage effects, enabling accurate measurements even during the settling interval
Solution Approach 2:
The system changes the parameter representation by transforming raw samples into adjusted samples using the settling profile. This parameter transformation removes the drift component and spectral leakage effects, converting the problematic settling-period samples into corrected measurements that maintain precision while enabling earlier analysis
3Measurement precision
If a longer settling time is implemented, then measurement precision is improved, but loss of time increases significantly
Solution Approach 1:
The system makes the useful action continuous by collecting samples throughout the settling interval rather than waiting for settling to complete. By continuously capturing data and computationally correcting it using the settling profile, the system eliminates idle wait time while maintaining measurement quality through ongoing computational processing
Data Source
AI summary
A test system that provides an output signal for analysis without requiring the test hardware to be idle during a settling interval. The test system includes a preprocessor that identifies the near-DC drift that occurs in the output signal and then adjusts the output signal to remove the near-DC drift. A set of values representing the near-DC drift at each of multiple times during the acquisition of a signal for analysis may be computed and used to model a settling profile of the signal by fitting a curve to the set of values. The model of the settling profile may then be subtracted from samples representing the output signal to provide an adjusted signal for further analysis.