Backside Illumination Semiconductor Thinning with High Boron Doping

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Solution Overview

Problem

Existing semiconductor apparatuses produced using backside illumination techniques have inadequate structural properties at and near the back surface of the semiconductor layer, leading to noise and performance issues due to insufficient boron concentration and surface damage during thinning processes.

Innovation Solution

A semiconductor apparatus with a boron-doped region extending 100 nm from the back surface, where the maximum boron concentration exceeds 1×10^20 atoms/cm^3, and a method involving mechanical grinding, wet etching, and chemical mechanical polishing to thin the semiconductor layer, ensuring improved planarity and reduced noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the semiconductor layer is thinned by physical polishing or wet etching to expose the back surface, then the thinning process can be completed, but the structure at and near the back surface is not sufficiently studied and properties are inadequate

Engineering Contradiction:
Improveback surface structure qualityVSAvoidsemiconductor apparatus performance
Core Design Contradiction:
Manufacturing precisionVSReliability

Solution Approach 1:

The patent applies parameter changes by introducing a high boron concentration region (more than 1×10^20 atoms/cm³) extending 100 nm from the back surface. This changes the doping parameter of the semiconductor layer to improve the structure at and near the back surface, thereby enhancing reliability and reducing noise in backside illumination semiconductor apparatus.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If wet etching is used to remove the semiconductor layer portion, then crystal defects can be removed and planarity is improved, but the process requires precise control of etching conditions

Engineering Contradiction:
Improvenoise reductionVSAvoidthinning process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing mechanical grinding before wet etching to remove the bulk of the semiconductor layer thickness. This preliminary removal reduces the amount of material that needs to be removed by the subsequent wet etching process, allowing for better control of the etching conditions and reducing process complexity while still achieving the desired crystal defect removal and planarity improvement.

Inventive Principle:
Principle #10Preliminary action

3Manufacturing precision

If chemical mechanical polishing is used after wet etching, then planarity is improved, but the amount of semiconductor layer removed by wet etching must be larger than by CMP

Engineering Contradiction:
Improvesurface planarityVSAvoidthinning process efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies segmentation by dividing the thinning process into three distinct stages: mechanical grinding for bulk removal, wet etching for intermediate removal and crystal defect elimination, and chemical mechanical polishing for final planarity improvement. This segmented approach allows each process to be optimized for its specific function, with the wet etching step removing a larger amount of material than CMP to ensure sufficient planarity improvement while maintaining productivity.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The approach significantly reduces noise and enhances the reliability and performance of the semiconductor apparatus by forming a high-boron-concentration region at the back surface and effectively removing crystal defects, improving the thinning process.

Implementation Method 1

the portion is removed by wet etching

Methodology Applied
Scientific EffectWet etching:

Implementation Method 2

chemical mechanical polishing for the semiconductor layer performed after the wet etching

Methodology Applied
Scientific EffectChemical mechanical polishing:

Implementation Method 3

mechanical grinding for the semiconductor layer

Methodology Applied
Scientific EffectMechanical grinding: Abrasion

Implementation Method 4

the semiconductor layer includes a region extending 100 nm from the back surface, the region having boron concentrations whose maximum value is more than 1×10^20 [atoms/cm3]

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS11605665B2Semiconductor apparatus and method for producing semiconductor apparatus
Publication Date: 2023.03.14 CANON KK
  • US11605665B2 patent drawing
  • US11605665B2 patent drawing
  • US11605665B2 patent drawing

AI summary

A semiconductor apparatus includes a semiconductor layer that includes a photoelectric conversion unit disposed between a front surface and a back surface and a transistor disposed at the front surface, and a dielectric film in contact with the back surface, wherein the semiconductor layer includes a region extending 100 nm from the back surface, the region having boron concentrations whose maximum value is more than 1×1020 [atoms/cm3].