Semiconductor Layout for Precise Through-Via Contact Formation

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Solution Overview

Problem

Existing semiconductor devices face challenges in achieving high reliability, high speed, and multifunctionality due to complex and integrated structures, particularly in the formation and dispersion of through-vias during back wiring processes, which affect contact smoothness between through-vias and lower source/drain contacts.

Innovation Solution

The semiconductor device incorporates a specific layout and pattern configuration, including active patterns, channel patterns, source/drain patterns, gate patterns, separation patterns, and through-vias, which allow for sufficient substrate removal, smooth formation of through-vias within gate cutting patterns, and reduced dispersion, enhancing contact between through-vias and lower source/drain contacts.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a separation pattern is added to control through-via formation, then manufacturing precision is improved, but device complexity increases

Engineering Contradiction:
Improvethrough-via formation precisionVSAvoidpattern structure complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The separation pattern divides the gate cutting pattern into distinct regions, creating separate through-via formation zones. This segmentation allows independent control of via formation in different areas, improving precision while managing complexity through systematic division

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The separation pattern is formed in advance during the gate cutting process, preparing the structure for subsequent through-via formation. This preliminary action ensures proper via alignment and reduces dispersion before the actual via creation step

Inventive Principle:
Principle #10Preliminary action

2Ease of operation

If substrate removal is extended to expose dummy source/drain patterns, then contact smoothness is improved, but manufacturing difficulty increases

Engineering Contradiction:
Improvecontact formation smoothnessVSAvoidsubstrate removal control
Core Design Contradiction:
Ease of operationVSEase of manufacture

Solution Approach 1:

The dummy source/drain patterns are positioned and prepared in advance on the substrate, serving as pre-defined targets for substrate removal. This preliminary placement guides the back wiring process and ensures smooth contact formation

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The dummy source/drain patterns act as intermediary structures that facilitate controlled substrate removal. These patterns serve as reference points and protective elements during the removal process, making manufacturing easier while achieving smooth contacts

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If through-via dispersion is reduced for smoother contact, then reliability is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvecontact reliabilityVSAvoidthrough-via placement precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The separation pattern creates distinct through-via regions that are spatially segmented and controlled. This segmentation reduces dispersion by confining via formation to specific zones, improving reliability while managing precision requirements through structured division

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the gate cutting pattern are given different properties through the separation pattern. Areas requiring through-vias are locally distinguished from other regions, allowing optimized via placement and reduced dispersion for improved contact reliability

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20260082689A1Semiconductor device
Publication Date: 2026.03.19 SAMSUNG ELECTRONICS CO LTD
  • US20260082689A1 patent drawing
  • US20260082689A1 patent drawing
  • US20260082689A1 patent drawing

AI summary

A semiconductor device includes an active pattern spaced apart in a first direction, and extending in a second direction different from the first direction; a lower channel pattern and a lower source/drain pattern located on the active pattern and alternately arranged in the second direction; an upper channel pattern on the lower channel pattern, and an upper source/drain pattern on the lower source/drain pattern; a gate pattern extending in the first direction and located on the lower channel pattern and the upper channel pattern; a separation pattern located between one of the lower source/drain pattern and the upper source/drain pattern and another of the lower source/drain pattern and the upper source/drain pattern in the second direction; and a gate cutting pattern extending in the second direction across the gate pattern to separate the gate pattern.