Semiconductor Device Through Via Layer Connection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor device manufacturing methods face challenges in efficiently connecting and forming transistors across multiple layers without degrading existing silicide films, leading to increased parasitic resistance and power consumption, and requiring complex alignment and high-temperature processes.
Innovation Solution
The semiconductor device employs a Through Via (TV) technology to connect transistors across layers using contact plugs and through-holes, forming source/drain regions at lower temperatures with polygermanium or other semiconductor substrates like indium gallium arsenic or indium gallium zinc oxide, avoiding damage to existing silicide films and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-temperature annealing is used to form source/drain regions, then electrical conductivity is improved, but existing silicide films are damaged
Solution Approach 1:
The patent changes the temperature parameter from high-temperature annealing to low-temperature processes (e.g., laser annealing at focused temperatures or thermal annealing below 450°C). This allows source/drain region formation without damaging the silicide films, resolving the contradiction between achieving good electrical conductivity and preserving silicide film integrity
Solution Approach 2:
The patent replaces conventional thermal annealing with alternative methods such as laser annealing or selective epitaxial growth. These methods provide localized heating or controlled material deposition that achieves the desired electrical properties without subjecting the entire structure to high temperatures that would damage silicide films
2Productivity
If conventional planar cell structures are stacked to increase integration density, then device capacity is improved, but alignment precision requirements increase
Solution Approach 1:
The patent divides the device into separate layers (first cell layer, second cell layer) with through-holes penetrating between them. Each layer can be formed and processed independently, then connected via through-holes. This segmentation allows each layer to be manufactured with standard precision, avoiding the need for ultra-precise alignment between layers
Solution Approach 2:
The through-holes act as intermediaries connecting the first and second cell layers. These through-holes provide a straightforward geometric feature that can be aligned relatively easily between layers, serving as a mediator that simplifies the alignment process compared to requiring precise alignment of complex transistor structures
3Reliability
If through-holes are formed to connect transistors across layers, then parasitic resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent combines the formation of through-holes with the formation of contact regions and source/drain structures in an integrated process. The through-holes are formed during the same processing steps used to create other critical features, merging multiple functions into a single manufacturing sequence that reduces overall complexity
Solution Approach 2:
The through-holes serve multiple functions: they provide electrical connection between layers, define contact regions, and establish source/drain structures. This multi-functionality reduces the total number of separate manufacturing steps needed, offsetting the apparent complexity by consolidating multiple purposes into a single structural feature
Data Source
AI summary
According to one embodiment, A semiconductor device includes: a first semiconductor layer; and a plurality of first transistors including a plurality of first gate structures provided on the first semiconductor layer, a first channel region provided in the first semiconductor layer and under the first gate structure, and a plurality of first diffusion regions provided in the first semiconductor layer in a manner to sandwich the first channel region.