Semiconductor Device Trench Opening Design for Carrier Extraction

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Solution Overview

Problem

In semiconductor devices with insulated gate bipolar transistors (IGBTs), carrier accumulation at the shorter portions of gate trench portions leads to increased carrier density, which affects switching performance and efficiency.

Innovation Solution

A semiconductor device design featuring a semiconductor substrate with a first trench portion and a dummy semiconductor region, where the interlayer insulating film has specific openings that connect the emitter electrode and the dummy semiconductor region, with the first opening closer to the outer end of the dummy region and having a larger area than other openings, to reduce carrier density at the shorter trench portion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If openings are provided in the interlayer insulating film to connect the emitter electrode and the dummy region, then carrier extraction is improved, but carrier accumulation occurs at the shorter portion of the gate trench portion

Engineering Contradiction:
Improvecarrier extractionVSAvoidcarrier density at shorter portion
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by making the first opening (closest to the outer end of the dummy region) have a larger area than other openings. This non-uniform opening design creates different carrier extraction capabilities at different locations, with the larger first opening providing enhanced carrier extraction at the shorter portion where carrier accumulation occurs, while other openings maintain standard extraction capability.

Inventive Principle:
Principle #3Local quality

2Quantity of substance

If the first opening has a larger area than other openings, then carrier density at the shorter trench portion is reduced, but device complexity increases

Engineering Contradiction:
Improvecarrier density distributionVSAvoidopening area variation
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent implements local quality by varying the area of the first opening relative to other openings. Specifically, the first opening has a larger area to target the carrier accumulation problem at the shorter portion, while other openings maintain standard dimensions. This localized modification optimizes carrier density distribution without requiring complete redesign of all openings.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11532737B2Semiconductor device
Publication Date: 2022.12.20 FUJI ELECTRIC CO LTD
  • US11532737B2 patent drawing
  • US11532737B2 patent drawing
  • US11532737B2 patent drawing

AI summary

A semiconductor device is provided, wherein a semiconductor substrate includes: a first trench portion provided from a front surface of the semiconductor substrate to a predetermined depth, and having a longer portion and a shorter portion as seen from above; and a first conductivity-type floating semiconductor region at least partially exposed on the front surface and surrounded by the first trench portion, an interlayer insulating film has openings to electrically connect an emitter electrode and the floating semiconductor region, the openings include: a first opening closest to an outer end of the floating semiconductor region in a direction parallel to the longer portion; and a second opening second closest to the outer end in the direction parallel to the longer portion, and a distance between the first opening and the second opening is shorter than a distance between any adjacent two of the openings other than the first opening.