Semiconductor Trench Structure for Oscillation Suppression
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Solution Overview
Problem
Semiconductor devices like FETs and IGBTs experience undesired oscillations in electrical characteristics during load switching, which need to be reduced or suppressed.
Innovation Solution
A semiconductor device design featuring a first and second transistor cell with electrically connected gate electrodes, along with a third trench extending deeper into the semiconductor body than the first and second trenches, filled with dielectric material to cover its bottom side and walls, which shifts dynamic electric field away from the transistor cells, reducing hot carrier injection and oscillations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional transistor cell structure with uniform trench depth is used, then the manufacturing process is simple, but oscillations occur during load switching and characteristic parameters drift
Solution Approach 1:
The device is segmented into multiple transistor cells (first transistor cell, second transistor cell, etc.) with gate electrodes in trenches. This segmentation allows independent control and optimization of each cell's electrical characteristics, reducing overall oscillations and improving stability of threshold voltage and switching speed parameters.
Solution Approach 2:
Different regions of the device have different trench depths - the first and second trenches have one depth while the third trench extends deeper. This local variation in trench depth creates different electric field distributions in different regions, suppressing oscillations and preventing characteristic parameter drift without requiring complete redesign of the entire structure.
2Reliability
If deeper trenches are introduced to suppress oscillations, then electrical stability improves, but manufacturing complexity increases
Solution Approach 1:
The trench structure is segmented into multiple types (first trenches, second trenches, third trenches) with different depths. This segmentation allows the manufacturing process to use standard trench formation techniques for most regions while applying deeper trenches only in specific locations where oscillation suppression is needed, balancing performance improvement with manufacturing feasibility.
Solution Approach 2:
Deeper third trenches are introduced only in specific regions between transistor cells where oscillation suppression is most beneficial, rather than increasing the depth of all trenches uniformly. This localized approach achieves the desired electrical stability while minimizing the overall manufacturing complexity and process changes required.
3Ease of manufacture
If uniform dielectric coverage is applied to all trenches, then the manufacturing process is straightforward, but dynamic electric field distribution is not optimized
Solution Approach 1:
The dielectric layer is applied with different thicknesses in different regions - thicker in the third deeper trenches and thinner in the first and second shallower trenches. This non-uniform dielectric coverage optimizes the electric field distribution locally in each region, suppressing dynamic avalanche breakdown and reducing reverse transfer capacitance effects while maintaining a relatively simple sequential deposition process.
Solution Approach 2:
The dielectric layer thickness parameter is varied across different trench regions to optimize electrical performance. By changing the dielectric thickness from thin (in first and second trenches) to thick (in third trenches), the invention achieves better electric field distribution and oscillation suppression while using standard dielectric deposition techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses or reduces undesired oscillations and drifting of characteristic parameters, such as threshold voltage and switching speed, by shifting dynamic avalanche breakdown and reducing reverse transfer capacitance, thereby improving the stability and performance of semiconductor devices.
Implementation Method 1
shifting dynamic electric field away from the transistor cells
Implementation Method 2
reducing reverse transfer capacitance
Data Source
AI summary
A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.