Semiconductor Device Trench Wiring for Contact Plug Formation
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Solution Overview
Problem
Current semiconductor device manufacturing techniques face challenges in microfabrication due to the difficulty in forming contacts between the source/drain electrodes and wiring layers in DRAM memory cells, particularly because the word line is formed on the substrate surface, requiring multiple contact plugs and complicating further miniaturization.
Innovation Solution
The semiconductor device and manufacturing method involve forming trenches of different depths in the substrate to position the word line and bit line within the substrate, allowing for closer proximity of the source/drain electrodes to the wiring, facilitating easier contact plug formation and enabling further microfabrication by reducing the number of layers and improving insulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the word line is formed on the substrate surface via a gate oxide film, then the MOS transistor can be properly formed, but the distance between the source/drain electrodes and wiring becomes large, making contact plug formation difficult
Solution Approach 1:
The patent applies dimensionality change by moving the bit line from the substrate surface to the same layer as the source/drain electrodes through trench formation. This spatial reconfiguration in the depth dimension reduces the distance between contact points, enabling easier contact plug formation while maintaining proper MOS transistor structure
Solution Approach 2:
The patent uses nesting by forming the bit line within a trench structure that is embedded in the substrate, placing it at the same depth level as the source/drain electrodes. This nested configuration allows direct electrical connection without requiring multiple contact plugs through intermediate layers
2Reliability
If multiple contact plugs are provided to connect source/drain electrodes to wiring layers, then electrical connection can be achieved, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The patent merges the bit line with the source/drain electrode layer by forming both structures at the same depth within the substrate. This consolidation eliminates the need for separate contact plugs to bridge different layers, reducing structural complexity while maintaining reliable electrical connections
Solution Approach 2:
The patent extracts the bit line from the traditional multi-layer wiring structure and repositions it to the same layer as the source/drain electrodes. This extraction simplifies the overall device structure by removing unnecessary intermediate contact plugs and insulating layers
3Reliability
If the wiring layer is provided above the word line, then proper electrical insulation can be achieved, but further microfabrication becomes difficult due to alignment requirements
Solution Approach 1:
The patent resolves the insulation problem by using lateral separation within the same layer rather than vertical stacking. The bit line and source/drain electrodes are formed at the same depth but separated in the planar dimension, eliminating alignment issues between layers while maintaining electrical insulation through proper spacing
Data Source
AI summary
A semiconductor device includes a plurality of MOS transistors and wiring connected to a source electrode or a drain electrode of the plurality of MOS transistors and, the wiring being provided in the same layer as the source electrode and the drain electrode in a substrate, or in a position deeper than a surface of the substrate.