Semiconductor Structure With TSV Bonding for Precise Wafer Alignment

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Solution Overview

Problem

Existing semiconductor manufacturing processes face challenges in efficiently integrating through silicon vias (TSVs) into semiconductor devices, particularly in achieving precise alignment and electrical connectivity during wafer-level packaging, which affects the overall performance and yield of semiconductor devices.

Innovation Solution

A method involving the formation of through silicon vias (TSVs) in the semiconductor substrate, followed by fusion bonding with a reclaim silicon substrate, and subsequent planarization processes to create integrated circuit components, enabling precise alignment and electrical connectivity through hybrid bonding techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If through silicon vias (TSVs) are integrated into semiconductor devices during wafer-level packaging, then electrical connectivity is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical connectivityVSAvoidmanufacturing complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent performs preliminary actions by forming TSVs in the first substrate before bonding occurs, and preparing corresponding bonding pads and alignment features in advance. This preliminary structuring enables precise alignment and electrical connectivity without adding complexity to the bonding process itself, as the connectivity pathways are pre-established in the substrate architecture.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements nesting by integrating TSVs within the substrate structure, where conductive vias are embedded within the silicon substrate and interconnected with bonding pads and alignment features. This nested arrangement consolidates multiple functions (electrical connection, mechanical alignment, and structural support) into a single integrated substrate design, improving connectivity while managing manufacturing complexity through unified structure formation.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Ease of manufacture

If reclaim silicon substrates are used for fusion bonding, then manufacturing cost is reduced, but alignment precision may be affected

Engineering Contradiction:
Improvemanufacturing costVSAvoidalignment precision
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent introduces alignment features and bonding pads as intermediary elements between the reclaim silicon substrate and the semiconductor die. These intermediaries provide precise registration marks and bonding interfaces that enable accurate alignment even when using cost-effective reclaim substrates. The alignment features act as mediators that decouple the cost benefit of reclaim materials from the precision requirements of the final device assembly.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent employs parameter changes by modifying the physical and chemical properties of the substrate surfaces through deposition and patterning processes. By controlling surface roughness, adhesion properties, and geometric dimensions of alignment features, the patent maintains high alignment precision with reclaim substrates. The parameter optimization of bonding interfaces ensures that cost reduction from using reclaim materials does not compromise manufacturing precision.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If hybrid bonding techniques are employed, then integration of TSVs is enhanced, but process complexity increases

Engineering Contradiction:
Improveintegration of TSVsVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges multiple bonding mechanisms into a unified hybrid bonding process. By combining direct metal-to-metal bonding with dielectric-to-dielectric bonding in a single integrated process flow, the patent enhances TSV integration reliability. The merging of bonding techniques allows simultaneous formation of electrical connections and mechanical bonding interfaces, improving integration while managing process complexity through consolidated processing steps.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements universality by designing a hybrid bonding process that performs multiple functions simultaneously: electrical connection through TSV bonding, mechanical attachment through substrate bonding, and alignment registration through integrated alignment features. This multi-functional bonding approach enhances TSV integration reliability while reducing the number of separate process steps needed, thereby managing overall process complexity through versatile process design.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

Enhances the integration of TSVs, improving the electrical connectivity and reducing manufacturing costs by utilizing reclaim silicon substrates, thereby increasing the yield and reliability of semiconductor devices.

Implementation Method 1

fusion bonding with a reclaim silicon substrate

Methodology Applied
Scientific EffectFusion bonding: Welding

Data Source

PatentUS20260076223A1Semiconductor structure and method manufacturing the same
Publication Date: 2026.03.12 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20260076223A1 patent drawing
  • US20260076223A1 patent drawing
  • US20260076223A1 patent drawing

AI summary

A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.