Semiconductor Device With Variable Trace Width For Crack Resistance
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Solution Overview
Problem
In semiconductor devices with stacked memory chips, cracks can occur in the bonding layer due to thermal stress, which complicates impedance control for high-speed signals like PCIe, limiting the trace width and affecting electrical performance.
Innovation Solution
A semiconductor device design featuring a multilayer wiring substrate with a bonding layer and trace width variations, including a thicker trace width portion to reinforce the substrate and prevent crack propagation, while maintaining impedance control for high-speed signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the trace width is increased to reduce crack influence, then reliability improves, but impedance control for high-speed signals deteriorates
Solution Approach 1:
The trace width is varied locally along its length, being wider at portions where cracks are likely to occur and narrower at other portions. This local variation allows the trace to have enhanced crack resistance at critical locations while maintaining proper impedance control overall, resolving the contradiction between reliability and manufacturing precision.
2Manufacturing precision
If the trace width is decreased for impedance control, then electrical performance improves, but crack resistance deteriorates
Solution Approach 1:
The trace width is varied locally along its length, being wider at portions where cracks are likely to occur and narrower at other portions. This local variation allows the trace to have enhanced crack resistance at critical locations while maintaining proper impedance control overall, resolving the contradiction between reliability and manufacturing precision.
3Reliability
If the trace width is made variable, then crack resistance improves, but device complexity increases
Solution Approach 1:
The trace is segmented into multiple portions with different width characteristics - a first trace width portion and a second trace width portion. This segmentation approach allows the trace to achieve improved crack resistance through width variation while keeping the structural complexity manageable by dividing the trace into distinct functional segments rather than using continuous complex variations.
Data Source
AI summary
A semiconductor device includes: a multilayer wiring substrate including a plurality of wiring layers; a first semiconductor chip disposed on the wiring substrate; and a bonding layer bonding the first semiconductor chip to the wiring substrate. A trace formed on the wiring substrate includes a first trace width portion and a second trace width portion, a width of the first trace width portion being greater than the second trace width portion.


