Semiconductor Device Vertical Channel Segmentation
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Solution Overview
Problem
Current semiconductor technologies face challenges in maximizing the number of memory cells within a predetermined area, as existing three-dimensional memory structures do not efficiently utilize space to increase memory density.
Innovation Solution
The semiconductor device employs vertically stacked channel layers and conductive layers, with charge storage layers in between, and pipe channel layers to separate and couple vertical channel layers, allowing for the formation of more memory cells by etching and separating these layers before forming the bit line, thereby doubling the memory capacity within the same area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional memory structures are used to increase memory cells per area, then memory density improves, but space utilization efficiency deteriorates
Solution Approach 1:
The vertical channel layer is divided into two separate channel layers (first and second vertical channel layers) that are alternately arranged. This segmentation allows each channel layer to be independently surrounded by its own conductive layers, effectively doubling the number of memory cells that can be formed within the same footprint area while maintaining efficient space utilization.
Solution Approach 2:
The patent transitions from a single vertical channel structure to multiple vertically stacked channel layers arranged in an alternating pattern. By utilizing the vertical dimension more effectively and creating alternating first and second vertical channel layers, the structure increases memory cell capacity in the vertical direction while maintaining horizontal space efficiency.
2Quantity of substance
If more memory cells are stacked vertically, then memory capacity increases, but manufacturing complexity increases
Solution Approach 1:
The memory structure is segmented into repeating units of first and second vertical channel layers, each with their own conductive layers. This modular segmentation simplifies manufacturing by allowing repeated application of the same formation processes for each unit, rather than creating a single complex multi-layer structure.
Solution Approach 2:
Adjacent first and second vertical channel layers share common conductive layers and charge storage layers between them. This merging approach reduces the total number of discrete layers that would otherwise be required, simplifying the manufacturing process while still achieving doubled memory capacity.
Data Source
AI summary
A semiconductor device includes a common source region formed in a semiconductor substrate, a bit line formed over the semiconductor substrate, first and second vertical channel layers coupled between the bit line and the common source region, wherein the first and second vertical channel layers are alternately arranged on the semiconductor substrate, first conductive layers stacked over the semiconductor substrate to surround one side of the first vertical channel layer, second conductive layers stacked over the semiconductor substrate to surround one side of the second vertical channel layer, and a charge storage layer formed between the first vertical channel layer and the first conductive layers and between the second vertical channel layer and the second conductive layers.