3D Semiconductor Device Vertical Channel Stacking
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Solution Overview
Problem
Current semiconductor devices face challenges in reducing the area of the cell array region, which affects the degree of integration and operational reliability, particularly in three-dimensional semiconductor devices with complex memory cell structures.
Innovation Solution
The semiconductor device incorporates first and second channel layers with a longitudinal sectional structure that narrows towards the lower portion, word lines stacked above, and select lines that surround the channel layers, along with a manufacturing method involving the formation of stack structures, isolation insulating layers, and slits to separate patterns, allowing for efficient electrical connection and isolation, thereby reducing the cell array area without expanding the horizontal space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the cell array area is reduced to improve integration density, then the degree of integration increases, but the operational reliability deteriorates due to insufficient space for proper electrical isolation and connections
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional vertical architecture. Memory strings extend vertically through multiple stacked layers, allowing the cell array to utilize the third dimension (height) for storage capacity. This vertical stacking enables higher integration density within the same footprint area while maintaining adequate horizontal spacing for electrical isolation structures.
Solution Approach 2:
The patent implements nested structures where select lines are positioned between stacked memory string groups, and isolation structures are integrated within the vertical stack. The first and second select lines are nested between first and second groups of memory strings, with isolation structures positioned between adjacent memory strings. This nesting allows multiple functional elements to occupy overlapping spatial regions, reducing the overall cell array area while preserving necessary electrical isolation.
2Area of moving object
If the horizontal space is reduced to improve integration density, then the area efficiency increases, but the manufacturing complexity increases due to tighter process tolerances
Solution Approach 1:
The patent divides the memory array into distinct groups of memory strings separated by isolation structures. First and second groups of memory strings are positioned between select lines, with isolation structures between adjacent strings. This segmentation creates modular units that can be manufactured with standard process tolerances, avoiding the need for extremely tight tolerances that would result from attempting to pack all structures uniformly in a reduced horizontal space.
Solution Approach 2:
By moving isolation and select structures into the vertical dimension rather than requiring them all in the horizontal plane, the patent reduces horizontal space requirements without compromising manufacturability. The vertical stacking of memory strings and positioning of select lines between stacks allows adequate horizontal spacing to be maintained for proper fabrication processes.
3Area of moving object
If the select line spacing is reduced to improve integration density, then the area utilization increases, but the electrical isolation effectiveness deteriorates
Solution Approach 1:
The patent positions isolation structures in the vertical dimension between stacked memory strings, rather than requiring increased horizontal spacing between select lines. The isolation structures extend vertically between adjacent memory strings, providing effective electrical isolation while allowing select lines to be positioned closer together in the horizontal plane, thereby improving area utilization.
Solution Approach 2:
The isolation structures serve as intermediary elements positioned between adjacent memory strings and between select lines. These structures provide the necessary electrical isolation function, enabling the select lines to be spaced closer together without compromising isolation effectiveness. The intermediaries allow tighter packing of active structures while maintaining functional requirements.
Data Source
AI summary
A semiconductor device includes a first channel layer and a second channel layer, each extending from an upper portion to a lower portion; and word lines stacked toward the upper portion from the lower portion, the word lines spaced apart from each other, the word lines each extending to surround the first channel layer and the second layer; a first lower select group surrounding a portion of the first channel layer that further protrudes toward the lower portion than the word lines; and a second lower select group surrounding a portion of the second channel layer that further protrudes toward the lower portion than the word lines.