Semiconductor Device with Vertical Lead Routing and Outer Bumps
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing thickness due to the need for a minimum distance between leads and semiconductor chips for connection, which also limits the thickness of the elastomer and results in increased device thickness.
Innovation Solution
The solution involves a wiring circuit board with leads extending from one surface and bumps positioned outside the chip mount region, allowing for a larger distance between the wiring layer and semiconductor chip, reducing the need for stress-relieving die attach material and enabling thinner semiconductor devices by securing the necessary connection distance for leads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between leads and semiconductor chip is increased to ensure proper connection, then connection reliability is improved, but device thickness increases
Solution Approach 1:
The patent applies dimensionality change by routing leads through the thickness direction (z-axis) of the substrate rather than maintaining them in the planar direction (x-y plane). Leads are formed to extend from the front surface, pass through openings in the substrate, and connect to electrode pads on the semiconductor chip from the rear surface. This vertical routing through the substrate thickness enables sufficient lead length for reliable connection while keeping the overall device thickness minimized, as the leads utilize the third dimension for their path.
2Reliability
If thick elastomer is used for stress relaxation, then stress concentration on solder bumps is reduced, but device thickness increases
Solution Approach 1:
The patent extracts and removes the thick elastomer stress relaxation layer from the device structure. Instead of using a thick compressible layer to absorb thermal expansion differences, the design relies on the flexibility of the substrate itself and the routing of leads through substrate openings to accommodate stress. This elimination of the thick elastomer layer directly reduces device thickness while maintaining stress relaxation through alternative means.
Solution Approach 2:
The patent changes the material parameter approach by substituting a thick elastomer layer with a thinner flexible substrate material that has appropriate mechanical properties. The substrate is designed with controlled flexibility to provide stress relaxation without requiring the thickness of traditional elastomer layers. This parameter change in material selection and thickness enables both stress relaxation and reduced overall device thickness.
3Reliability
If leads are routed through the substrate, then connection distance is secured, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple functions into the substrate structure itself. The substrate simultaneously serves as the mechanical support, the stress relaxation element, and the routing pathway for leads. By integrating lead routing through substrate openings rather than requiring separate channels or complex multi-layer constructions, the design simplifies manufacturing while ensuring reliable lead connections. The openings are formed directly in the substrate during fabrication, combining structural and electrical functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for a reduction in the thickness of semiconductor devices and stacked devices by eliminating the need for thick stress-relieving materials and minimizing shearing deformation, while ensuring reliable lead connections.
Implementation Method 1
A die attach material as a connecting member that connects the semiconductor chip to the wiring circuit board is provided between the wiring circuit board and the semiconductor chip
Implementation Method 2
an elastomer for relaxing stress concentration on the solder bumps due to the difference between the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of a mount substrate
Implementation Method 3
stress concentration on the solder bumps due to the difference between the thermal expansion coefficient of the semiconductor chip and the thermal expansion coefficient of a mount substrate
Implementation Method 4
Solder bumps are connected to bump lands in the wiring on the flexible wiring circuit board
Data Source
AI summary
A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted.