Semiconductor Device With Vertical Well Region For Voltage Resistance
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Solution Overview
Problem
Conventional lateral-type semiconductor devices face challenges in reducing electric field concentration at the edge of the well region, leading to reduced voltage resistance due to the inability to effectively manage current flow and impurity concentration differences.
Innovation Solution
A semiconductor device with a substrate, drift region, well region, source region, and gate structure where the edge of the well region extends into the substrate, utilizing a semi-insulating or insulating substrate with a higher impurity concentration in the drift region to enhance voltage resistance and channel width, and incorporating a gate groove and electrodes with a gate insulating film to control current flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If a lateral-type semiconductor device structure is used to increase channel width, then the channel width can be increased by defining it through drift region depth, but electric field concentration occurs at the well region edge leading to reduced voltage resistance
Solution Approach 1:
The patent transitions from a conventional planar well region to a vertical well region that extends in the depth direction perpendicular to the substrate surface. This dimensional change allows the well region edge to be positioned deeper inside the substrate, away from the surface where electric field concentration occurs, thereby resolving the contradiction between maintaining lateral current flow and preventing electric field concentration at the well edge.
Solution Approach 2:
The patent performs preliminary doping to form a high-impurity-concentration drift region before forming the well region. This preliminary action creates a favorable impurity concentration distribution that suppresses electric field concentration at the well region edge, enabling the vertical well structure to achieve both increased channel width and improved voltage resistance.
2Device complexity
If the well region edge is positioned within the drift region, then the device structure is simplified, but electric field concentration occurs reducing overall voltage resistance
Solution Approach 1:
The patent positions the well region edge in the vertical dimension by extending the well region in the depth direction, rather than keeping it confined to the horizontal plane. This allows the well edge to be located deeper in the substrate where it does not cause electric field concentration, maintaining structural simplicity while improving voltage resistance.
3Reliability
If a guard ring is added to prevent electric field concentration, then voltage resistance improves, but the device cannot be implemented in lateral-type structures
Solution Approach 1:
The patent segments the drift region into two distinct functional zones: a first drift region with higher impurity concentration near the surface that suppresses electric field concentration, and a second drift region with lower impurity concentration that enables high breakdown voltage. This segmentation replaces the need for guard rings while maintaining compatibility with lateral-type device structures.
Solution Approach 2:
The patent applies different impurity concentrations to different spatial locations within the drift region. The first drift region has higher impurity concentration specifically at locations where electric field concentration would occur, while the second drift region maintains lower impurity concentration for optimal voltage blocking, creating local quality variations that eliminate the need for guard rings.
Data Source
AI summary
The semiconductor device includes: a substrate, an n-type drift region formed on a main surface of the substrate; a p-type well region, an n-type drain region and an n-type source region each formed in the drift region to extend from a second main surface of the drift region opposite to the first main surface of the drift region in contact with the substrate in a direction perpendicular to the second main surface; a gate groove extending from the second main surface in the perpendicular direction and penetrating the source region and the well region in a direction parallel to the first main surface of the substrate; and a gate electrode formed on a surface of the gate groove with a gate insulating film interposed therebetween, wherein the drift region has a higher impurity concentration than the substrate, and the well region extends to the inside of the substrate.