Semiconductor Heat Dissipation via Non-Penetrating Vias

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Solution Overview

Problem

Existing semiconductor devices face reliability and design limitations due to stress-induced cracks and reduced water resistance from polishing methods, and increased interconnection delays from through vias used for heat dissipation, which restrict the layout and efficiency of heat dissipation.

Innovation Solution

A semiconductor device design featuring second vias that do not penetrate the sealing portion, allowing for efficient heat dissipation without contacting the substrate or semiconductor chip, providing a high degree of freedom in heat dissipation and reducing stress, while maintaining reliability and performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Temperature

If polishing is used to expose the semiconductor chip for heat dissipation, then heat dissipation is improved, but reliability deteriorates due to stress-induced cracks and reduced water resistance

Engineering Contradiction:
Improveheat dissipationVSAvoidreliability
Core Design Contradiction:
TemperatureVSReliability

Solution Approach 1:

The patent extracts the heat dissipation function from the semiconductor chip itself and relocates it to the sealing portion. By forming heat dissipation holes in the sealing portion and filling them with conductive material, the heat dissipation path is separated from the chip structure, allowing heat to be dissipated without exposing or stressing the chip.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces an intermediary structure (the heat dissipation holes filled with conductive material in the sealing portion) between the semiconductor chip and the external environment. This intermediary serves as a heat transfer medium that conducts heat away from the chip without requiring direct exposure of the chip surface, thus maintaining reliability while achieving heat dissipation.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Temperature

If through vias are formed in the semiconductor chip for heat dissipation, then heat dissipation is improved, but device complexity increases due to restricted layout design and increased interconnection delay

Engineering Contradiction:
Improveheat dissipationVSAvoiddevice complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent removes the heat dissipation function from the semiconductor chip interior (where through vias would be required) and relocates it to the sealing portion. This extraction eliminates the need for through vias that would complicate the chip's internal layout and increase interconnection delay, while still providing effective heat dissipation through the sealing portion's heat dissipation holes.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively improves heat dissipation without compromising the reliability or performance of the semiconductor device, allowing for flexible layout designs and reduced noise release, enhancing the stability and efficiency of the semiconductor chip operation.

Implementation Method 1

a plurality of second vias located inwardly from the first vias and extending from the surface of the sealing portion in the thickness direction of the sealing portion to such a depth that the second vias do not penetrate the sealing portion

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS9219021B2Semiconductor device including heat dissipating structure
Publication Date: 2015.12.22 PANASONIC SEMICON SOLUTIONS CO LTD
  • US9219021B2 patent drawing
  • US9219021B2 patent drawing
  • US9219021B2 patent drawing

AI summary

A semiconductor device includes a substrate serving as a base and having a surface on which electrodes are provided, a semiconductor chip mounted to the surface of the substrate, a sealing portion sealing the semiconductor chip and the surface of the substrate, first vias each penetrating the sealing portion in a thickness direction of the sealing portion to reach the electrodes on the surface of the substrate, external terminals connected to the first vias, and second vias provided near the semiconductor chip, extending to such a depth that the second vias do not penetrate the sealing portion, and insulated from the substrate and the semiconductor chip.