Semiconductor Via Plug Diameter Tapering for Pad Layout

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Solution Overview

Problem

In semiconductor devices formed by bonding wafers, the layout and interconnections of bonding pads are challenging to optimize for manufacturing cost and reliability, particularly in ensuring efficient electrical connections between chips while minimizing material usage and simplifying the formation of via plugs.

Innovation Solution

The semiconductor device incorporates a first chip with a control circuit and a second chip bonded using via plugs that decrease in diameter along their length, allowing for efficient electrical connections and material savings by forming these plugs before bonding, which facilitates preferable layout and interconnections of bonding pads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If via plugs are formed after bonding, then electrical connections between chips are ensured, but material usage increases and manufacturing complexity increases

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidmaterial usage

Core Design Contradiction:

ReliabilityVSLoss of substance

Solution Approach 1:

The via plugs are formed in the interlayer insulating film before the bonding process. This preliminary formation allows the plugs to be created when access to the bonding interface is easier, reducing material waste and simplifying the manufacturing process while ensuring reliable electrical connections after bonding

Inventive Principle:

Principle #10Preliminary action

2Reliability

If via plugs are formed after bonding, then electrical connections between chips are ensured, but manufacturing complexity and cost increase

Engineering Contradiction:

Improveelectrical connection reliabilityVSAvoidmanufacturing simplicity

Core Design Contradiction:

ReliabilityVSEase of manufacture

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

3Ease of manufacture

If bonding pads are laid out without optimization, then chip bonding is simplified, but manufacturing cost and reliability are compromised

Engineering Contradiction:

Improvebonding process simplicityVSAvoiddevice reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The device is divided into a first chip and a second chip that are bonded together. The via plugs are formed in the interlayer insulating film of the first chip before bonding, allowing independent optimization of each chip's bonding pad layout while ensuring reliable electrical connections through the pre-formed plugs

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS11063062B2Semiconductor device and method of manufacturing the same

Publication Date: 2021.07.13 KIOXIA CORP

AI summary

In one embodiment, a semiconductor device includes a first chip and a second chip. The first chip includes a first substrate, a control circuit provided on the first substrate, and a first pad provided above the control circuit and electrically connected to the control circuit. The second chip includes a second pad provided on the first pad, a plug provided above the second pad, extending in a first direction, and including a portion that decreases in diameter in a cross-section perpendicular to the first direction with increasing distance from the first substrate, and a bonding pad provided on the plug, intersecting with the first direction, and electrically connected to the second pad by the plug.