Real-time Fault Detection in Semiconductor Wafer Processing

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Solution Overview

Problem

Semiconductor manufacturing processes face challenges in detecting faults in real-time during wafer processing, leading to wasted resources and time, as defects are typically identified only after the manufacturing is complete.

Innovation Solution

A method involving the execution of a wafer recipe with control inputs and timing constraints, monitoring sensor outputs, and providing them to trained models to identify fault conditions, generating a fault output when anomalies are detected, and using recurrent neural networks with long short-term memory (LSTM) to classify and adapt to new fault patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If fault detection is performed only after manufacturing is complete, then testing is simpler and less complex, but time and resources are wasted processing defective wafers through all manufacturing steps

Engineering Contradiction:
Improvetime wasted processing defective wafersVSAvoidcomplexity of fault detection system
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent implements preliminary fault detection during the manufacturing process by monitoring sensor data in real-time and using trained models to identify fault conditions before the wafer completes all manufacturing steps. This allows early termination of processing for defective wafers, preventing waste of time and resources while maintaining relatively simple implementation through existing sensor networks and machine learning models.

Inventive Principle:
Principle #10Preliminary action

2Productivity

If real-time monitoring and classification of fault conditions is implemented during manufacturing, then time and resources are saved by early detection, but the complexity of the processing system increases

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidcomplexity of monitoring and classification system
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system performs self-service by automatically monitoring sensor data, classifying fault conditions using trained machine learning models, and identifying defective wafers without requiring complex manual intervention. The models are trained on historical data and automatically adapt to different fault patterns, enabling the system to improve its own performance over time while maintaining manufacturing efficiency.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent implements feedback mechanisms where sensor data from the manufacturing process is continuously monitored and fed into classification models that provide real-time fault detection. The system learns from past fault conditions and improves its detection accuracy over time, creating a self-improving feedback loop that enhances productivity without proportionally increasing system complexity.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If multiple classification models are used to improve fault detection accuracy, then fault recognition precision improves, but computational requirements and processing time increase

Engineering Contradiction:
Improvefault detection accuracyVSAvoidcomputational energy consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent segments the fault detection task by using multiple specialized classification models, each trained to detect specific types of fault conditions. This segmentation allows the system to achieve high overall detection accuracy by combining the strengths of individual models while managing computational load through parallel processing and early termination when faults are detected.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11556117B2Real-time anomaly detection and classification during semiconductor processing
Publication Date: 2023.01.17 APPLIED MATERIALS INC
  • US11556117B2 patent drawing
  • US11556117B2 patent drawing
  • US11556117B2 patent drawing

AI summary

A method of detecting and classifying anomalies during semiconductor processing includes executing a wafer recipe a semiconductor processing system to process a semiconductor wafer; monitoring sensor outputs from a sensors that monitor conditions associated with the semiconductor processing system; providing the sensor outputs to models trained to identify when the conditions associated with the semiconductor processing system indicate a fault in the semiconductor wafer; receiving an indication of a fault from at least one of the models; and generating a fault output in response to receiving the indication of the fault.