Semiconductor Wafer with Replicated IC Modules and Cross-Wafer Connections
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Solution Overview
Problem
Conventional methods for providing different memory configurations in integrated circuits either result in lower gross margins due to 'phantoming' high-end applications or incur high costs by creating separate silicon mask sets for each product within a product range.
Innovation Solution
A semiconductor wafer with replicated integrated circuit modules and inter-module cross-wafer electrical connections allows for the creation of IC dies with varying configurations by cutting along specific scribe lines, enabling both high-end and low-end applications without the need for separate silicon mask sets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate silicon mask sets are created for each memory configuration, then optimal cost efficiency is achieved for each product, but the overall product cost increases due to multiple mask set creations
Solution Approach 1:
The semiconductor wafer is divided into multiple scribe lines that can be selectively removed or retained, allowing different configurations of replicated IC modules to be obtained from a single wafer. This segmentation enables a single mask set to produce multiple product variants by controlling which scribe lines are removed, resolving the contradiction between per-product cost efficiency and overall product cost.
Solution Approach 2:
A single semiconductor wafer design with replicated IC modules and selective scribe lines serves multiple product configurations simultaneously. The same mask set can produce high-end products (with more memory modules) and low-end products (with fewer memory modules) by varying the scribe line removal pattern, achieving universality across different product specifications.
2Ease of manufacture
If 'phantoming' is used to disable unrequired memory for lower-end applications, then a single silicon mask set is created, but lower gross margin is achieved for lower-end products
Solution Approach 1:
Instead of disabling unrequired memory through phantoming, the invention extracts the exact number of functional IC modules needed for each product configuration by selectively removing specific scribe lines. This allows lower-end products to have only the necessary memory modules physically present and functional, eliminating the waste associated with phantoming while maintaining single mask set benefits.
Solution Approach 2:
The scribe line configuration is made dynamic and adjustable after wafer fabrication. By selectively removing or retaining specific scribe lines based on the target product configuration, the same wafer design can be adapted to different market segments, enabling lower-end products to achieve optimal gross margins without requiring separate mask sets.
3Adaptability or versatility
If replicated IC modules are arranged on a semiconductor wafer with inter-module cross-wafer electrical connections, then flexible fabrication of different memory configurations is enabled, but the wafer structure and fabrication process become more complex
Solution Approach 1:
The wafer is segmented into multiple identical replicated IC modules arranged in a systematic pattern with standardized scribe lines between them. This regular segmentation simplifies the fabrication process compared to custom designs, while the selective removal of specific scribe lines provides the needed flexibility for different configurations.
Solution Approach 2:
The invention changes the parameter of scribe line presence/absence rather than altering the fundamental wafer structure or IC module design. This approach maintains structural simplicity while achieving configuration flexibility through a binary parameter change (scribe line removed or retained) that can be applied post-fabrication.
Data Source
AI summary
There is provided a semiconductor wafer comprising a plurality of replicated IC modules. Each replicated IC module is capable of forming an individual IC die. The semiconductor wafer further comprises inter-module cross-wafer electrical connections, and the replicated IC modules are further arranged to be cut into IC dies comprising multiple replicated IC modules.There is further provided a method of fabricating an IC die. The method comprises fabricating such a semiconductor wafer, determining a required configuration of replicated IC modules, identifying inter-module boundaries along which to cut the semiconductor wafer to achieve the required configuration of replicated IC modules, and cutting the semiconductor wafer along the identified inter-module boundaries to produce at least one IC die comprising the required configuration of replicated IC modules.