Semiconductor Wafer Through Via Direct Bonding
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Solution Overview
Problem
Conventional semiconductor structures face high manufacturing costs and reduced yield rates due to complex processes and difficulties in underfill encapsulation of bumps between wafers, which are exacerbated by the need for multiple redistribution layers and through vias in each chip.
Innovation Solution
A semiconductor structure and method where wafers or chips are connected using a single through via, eliminating the need for multiple redistribution layers and bumps, by forming a groove to expose conductive pads and creating a through via for direct electrical connection, thereby simplifying the process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple redistribution layers and through vias are formed in each chip to electrically connect chips, then electrical connection is achieved, but manufacturing cost increases
Solution Approach 1:
The patent merges the electrical connection function into a single through via that penetrates multiple chips, eliminating the need for separate redistribution layers in each chip. This consolidation reduces the number of manufacturing steps and materials required, directly lowering manufacturing cost while maintaining electrical connectivity.
Solution Approach 2:
The invention extracts and eliminates the redundant redistribution layers from the conventional structure, retaining only the essential through via for electrical connection. This simplification removes unnecessary manufacturing complexity and cost while preserving the core electrical connection function.
2Volume of moving object
If the pitch between bumps is narrowed to reduce product size, then product size is reduced, but underfill cannot properly encapsulate the bumps
Solution Approach 1:
The patent removes the bumps and underfill encapsulation requirement from the design by implementing direct wafer-to-wafer or chip-to-chip bonding through the through via structure. This elimination of the underfill process entirely resolves the encapsulation problem while maintaining compact product dimensions.
Solution Approach 2:
Instead of using bumps with underfill encapsulation, the invention inverts the approach by using direct surface bonding through exposed conductive pads. This alternative methodology achieves electrical connection and mechanical bonding without requiring the problematic bump-and-underfill structure.
3Reliability
If multiple redistribution layers and through vias are formed in each chip, then electrical connection is achieved, but the manufacturing process becomes complex
Solution Approach 1:
The patent combines multiple electrical connection functions into a single through via structure that penetrates through chips, eliminating the need for separate redistribution layers in each chip. This merging of functions significantly simplifies the manufacturing process by reducing the number of deposition, etching, and alignment steps required.
Solution Approach 2:
The invention inverts the conventional approach by forming the through via first and then creating conductive pads on the exposed surfaces, rather than building up multiple redistribution layers. This inverted sequence of operations simplifies the manufacturing process while achieving the same electrical connection objective.
4Reliability
If underfill is used to encapsulate bumps between wafers, then wafer connection is achieved, but yield rate decreases due to filling difficulties
Solution Approach 1:
The patent extracts and eliminates the underfill encapsulation step entirely by using direct bonding between exposed conductive pads on adjacent chips or wafers. This removal of the underfill process completely avoids the filling difficulties and associated yield losses while maintaining reliable wafer connection.
Solution Approach 2:
Instead of using underfill to seal and protect bump connections, the invention inverts the approach by exposing conductive pads and forming direct bonds without any encapsulation material. This alternative connection methodology eliminates the yield-reducing underfill process while achieving reliable electrical and mechanical connection.
Data Source
AI summary
The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer. Therefore, the wafers are penetrated and electrically connected by forming only one conductive via, which leads to a simplified process and a low manufacturing cost.