Semiconductor Device Well Structure for Latch-up Suppression
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Solution Overview
Problem
In semiconductor devices, the coexistence of high-voltage and low-voltage transistors leads to issues such as latch-up due to parasitic NPN bipolar transistors, where the current amplification factor is high, and punch-through occurs, making it difficult to downsize the device while maintaining reliability.
Innovation Solution
A semiconductor device structure is implemented with a deep fourth well of the same conductive type as the substrate between the second and third wells, increasing the impurity concentration of the parasitic bipolar transistor base, thereby suppressing latch-up and punch-through, and allowing for shallower first and second wells to prevent impurity diffusion and enable downsizing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the second n-well is formed deeply to prevent punch-through in high-voltage transistors, then punch-through is suppressed, but the first n-well and p-well for low-voltage transistors become shallower causing impurity diffusion and making downsizing difficult
Solution Approach 1:
The invention divides the well structure into multiple segments: a first n-well for low-voltage transistors, a second n-well for high-voltage transistors, and a newly introduced fourth n-well positioned between them. This segmentation allows each well to be optimized independently - the second n-well can be deep for punch-through suppression while the first n-well remains shallow to prevent impurity diffusion, resolving the contradiction between reliability and device size.
Solution Approach 2:
The fourth n-well acts as an intermediary structure between the first and second n-wells. It provides electrical isolation and prevents direct interaction between the low-voltage and high-voltage regions, allowing the second n-well to be formed deeply without causing impurity diffusion to the first n-well, thus enabling both punch-through suppression and downsizing.
2Reliability
If high-concentration impurity layers are formed at end portions of wells to suppress latch-up, then latch-up is reduced, but the base concentration of parasitic bipolar transistor is not sufficiently increased
Solution Approach 1:
The invention applies different impurity concentrations to different regions: the fourth n-well is formed with high impurity concentration specifically in the base region of the parasitic bipolar transistor, while maintaining appropriate impurity levels in other wells. This localized quality enhancement increases the base concentration where needed to suppress latch-up without unnecessarily increasing impurity concentration throughout the entire structure.
3Length of moving object
If shallow wells are used for low-voltage transistors to prevent impurity diffusion, then downsizing is enabled, but the current amplification factor of parasitic bipolar transistors increases causing latch-up
Solution Approach 1:
The fourth n-well serves as an intermediary that electrically isolates the shallow first n-well from the deep second n-well. This isolation prevents the formation of high-gain parasitic bipolar transistors that would cause latch-up, while allowing the first n-well to remain shallow for downsizing. The fourth n-well effectively decouples the size optimization from the latch-up prevention requirement.
Data Source
AI summary
According to the present invention, provided is a semiconductor device including: a p-type silicon substrate; a shallow n-well formed in the silicon substrate; a shallow p-well formed beside the shallow n-well in the silicon substrate; and a deep n-well which is formed beside the shallow p-well in the silicon substrate, and which is deeper than the shallow p-well. In addition, a deep p-well, which is deeper than the shallow p-well, is formed between the shallow p-well and the deep n-well in the silicon substrate.