Semiconductor Device Hole Supply via Well Pickup Layer
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Solution Overview
Problem
Three-dimensional non-volatile memory devices face challenges in supplying sufficient holes during erase operations, leading to performance issues with source select transistors due to gate-induced drain leakage (GIDL), which limits integration degree and erasing efficiency.
Innovation Solution
A semiconductor device structure with a source layer, well pickup layer, body structure, channel pillars, and contact layers that electrically connect the well pickup layer and source layer, allowing direct supply of holes to channel pillars during erase operations, thereby improving erasing efficiency and increasing integration degree by positioning the peripheral region under the cell region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If holes are supplied during erase operation in three dimensional non-volatile memory device, then erase operation is performed, but source select transistor performance deteriorates due to gate induced drain leakage (GIDL)
Solution Approach 1:
The device is divided into separate functional regions: a dedicated erase region with the well pickup layer for hole supply, and a separate source select transistor region. This segmentation allows erase operations to occur without GIDL affecting the source select transistor performance, as the two functions are spatially separated.
Solution Approach 2:
The well pickup layer acts as an intermediary structure that enables hole supply during erase operations while preventing direct GIDL effects on the source select transistor. It serves as a mediator between the erase function and the transistor, allowing the beneficial hole supply while blocking the harmful GIDL effect.
2Quantity of substance
If two dimensional memory device integration degree is improved, then storage capacity increases, but further improvements are limited
Solution Approach 1:
The patent transitions from two-dimensional planar memory structure to three-dimensional vertical stacking architecture. Multiple memory cell layers are stacked vertically above the substrate, enabling storage capacity expansion in the vertical dimension rather than being constrained by horizontal plane area, thus overcoming two-dimensional integration limits.
3Reliability
If contact layers are formed on side walls of body structure, then well pickup layer and source layer are electrically connected, but manufacturing process complexity increases
Solution Approach 1:
The contact layers are formed within side wall structures that are nested around the body structure. The contact layers are positioned inside the side wall regions, creating a nested configuration where the connection path is integrated within the existing structural framework rather than requiring separate external connection structures.
Data Source
AI summary
There is provided a semiconductor device. The semiconductor device includes a source layer, a well pickup layer formed on the source layer, a body structure formed on the well pickup layer and including a well region contacting the well pickup layer and first junctions formed on side walls of the body structure, channel pillars contacting the body structure and protruding from the body structure, and contact layers formed on the side walls of the body structure and electrically connecting the body structure and the well pickup layer.