Semiconductor Wiring Layout With Aggregated Via Plugs
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Solution Overview
Problem
In semiconductor devices with multilayer wiring structures, efficiently laying out wiring tracks between layers is challenging due to the need for via plugs, which can lead to increased layout area, signal delay, and increased man-hours for design, as well as difficulties in connecting lines between trunk and branch lines without causing overflow or requiring bypass wiring.
Innovation Solution
The semiconductor device employs a wiring structure where lines extend along multiple tracks in a layer, with via plug positions aggregated on one side, allowing for efficient provisioning of wiring tracks and reducing layout area, signal delay, and design complexity by optimizing the placement of via plugs to minimize wiring length and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via plugs are used to connect lines between wiring layers, then electrical connection between layers is achieved, but layout area increases and signal delay increases
Solution Approach 1:
Multiple via plugs are aggregated and merged into a single shared via plug that serves multiple lines simultaneously. This consolidation reduces the total number of via plugs needed, thereby decreasing layout area while maintaining electrical connection reliability for all connected lines.
Solution Approach 2:
A single via plug is designed to serve multiple functions by connecting multiple lines between wiring layers. This multi-functional via plug reduces the overall via plug count and layout area while achieving the necessary electrical connections for all lines.
2Reliability
If via plugs are used to connect lines between wiring layers, then electrical connection between layers is achieved, but signal delay increases
Solution Approach 1:
By merging multiple via plugs into a single shared via plug, the patent reduces the total number of via plug interfaces that signals must traverse. This consolidation shortens the overall signal path and reduces cumulative signal delay while maintaining reliable electrical connection between wiring layers.
3Adaptability or versatility
If via plug positions are distributed throughout the wiring layer, then connection flexibility is improved, but layout complexity and design time increase
Solution Approach 1:
The patent consolidates multiple via plug positions into aggregated locations, reducing layout complexity. The merged via plugs maintain connection flexibility by serving multiple lines, while the simplified layout structure reduces design time and manual effort.
4Reliability
If via plugs are placed to connect trunk and branch lines, then line connectivity is achieved, but overflow occurs and bypass wiring is required
Solution Approach 1:
The patent uses aggregated via plugs to connect trunk and branch lines in a consolidated manner, eliminating overflow issues. The merged via plug structure provides direct connectivity without requiring additional bypass wiring, thereby simplifying the overall wiring structure while maintaining reliable line connectivity.
Data Source
AI summary
A semiconductor device includes first and second wiring layers, and first and second via plugs. The first wiring layer has parallel tracks along which wirings are laid out, the tracks including first and second outer tracks and an inner track between the first and second outer tracks, the wirings including a first line laid out along the first outer track and having an end portion that is laid out along the first outer track, and a second line laid out along the inner track and having an end portion that is laid out along the first outer track. The first via plug is in contact with the end portion of the first line and extends between the first and second wiring layers, and the second via plug is in contact with the end portion of the second line and extends between the first and second wiring layers.