Semiconductor Wiring Alloy Layer for Void-Free Via Formation
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with copper (Cu) wiring and low dielectric constant films face issues such as recesses and projections on the side walls of connection holes due to elemental Cu scattering, leading to poor barrier film coverage, void formation, and reduced electromigration (EM) and stress migration (SM) resistance, especially as devices miniaturize.
Innovation Solution
Forming an alloy layer composed of a first metallic material, such as Cu, and a second metallic material, like Ta, on the surface of the wiring, which is then sputter etched to prevent aggregation and oxidation, ensuring better barrier film coverage and adhesion, and enhancing EM and SM durability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If sputter etching is performed on elemental Cu to form an anchor structure, then the wiring resistance is reduced by increasing the joint region between lower layer wiring and via, but recesses and projections are generated on the side wall of the connection hole due to Cu scattering and aggregation, leading to poor barrier film coverage
Solution Approach 1:
The patent changes the material parameter of the wiring from pure elemental Cu to an alloy containing Cu and another metal element. This parameter change prevents scattering and aggregation during sputter etching, eliminating recesses and projections on the connection hole side wall, thereby achieving smooth barrier film coverage while maintaining anchor structure formation for low wiring resistance
Solution Approach 2:
The patent uses a composite alloy material consisting of Cu and another metal element instead of pure Cu. This composite material combines the low resistance property of Cu with the scattering prevention property of the other metal element, resolving the contradiction between manufacturing precision and reliability
2Reliability
If elemental Cu is scattered during sputter etching, then the anchor structure is formed to reduce wiring resistance, but voids are generated in the via due to poor adhesion between barrier film and insulation layer
Solution Approach 1:
The patent changes the material composition parameter from pure Cu to an alloy, which prevents scattering and aggregation during sputter etching. This eliminates the root cause of poor barrier film adhesion and subsequent void formation, achieving both high reliability and void-free via structure
Solution Approach 2:
The patent converts the potentially harmful scattering effect into a beneficial deposit layer on the connection hole side wall. The alloy scattering products form a smooth, adherent layer that prevents void formation, transforming the harmful scattering into a protective feature
3Productivity
If the connection hole size is reduced for device miniaturization, then the degree of integration is enhanced, but the wiring resistance increases and the impact of scattering and aggregation becomes more significant
Solution Approach 1:
The patent changes the material parameter to an alloy that is inherently resistant to scattering and aggregation. This allows continued miniaturization of connection holes while maintaining manufacturing precision, as the alloy material does not suffer from the aggregation problems that plague pure Cu in small-scale features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents void formation and improves adhesion between the barrier film and insulation layer, enhancing the reliability of the wiring structure and enabling the production of high-performance CMOS devices with improved durability and reduced wiring resistance.
Implementation Method 1
the alloy layer is sputter etched, whereby the alloy is scattered and deposited on the side wall of the connection hole
Data Source
AI summary
A semiconductor device including a substrate, a metal wiring on the substrate, an insulation film on the substrate covering the metal wiring, a connection hole in the insulation film which extends to a portion of the metal wiring, a via in the connection hole, and an alloy layer. The metal wiring includes a first metallic material, the alloy layer comprises a portion of the metal wiring and a second metallic material which is different than the first metallic material, and the via extends to the alloy layer.