Semiconductor Wiring Board Segmentation for Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor element mounted wiring boards face challenges in reducing thickness and increasing performance, leading to defects during wiring layer formation that result in low fabrication yield due to the need for solder connections and the waste of resin-sealed semiconductor elements.
Innovation Solution
A method involving the preparation of a metal plate with an opening, attaching it to a support base, embedding a semiconductor element, forming an insulating layer, and stacking wiring layers on a temporary substrate to create a conductive bump connection, allowing for the connection of electrode terminals without the need for solder bumps, thus enabling the separation of defective substrates and improving yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If conventional bumpless mounting board structure is used with resin sealing and copper plating, then thickness reduction is achieved, but fabrication yield decreases due to defects in wiring layer formation
Solution Approach 1:
The invention divides the manufacturing process into two independent stages: first forming the chip sealed substrate with electrode terminals, then separately forming the wiring substrate with wiring layers and conductive bumps. This segmentation allows defects in wiring layer formation to be detected and corrected without wasting the chip sealed substrate, thereby improving fabrication yield while maintaining thickness reduction benefits.
Solution Approach 2:
The chip sealed substrate is prepared in advance with electrode terminals exposed on the sealing surface, before the wiring layers are formed. This preliminary action allows the substrate to be ready for connection while enabling subsequent inspection and correction of wiring layer defects, preventing yield loss from premature integration.
2Reliability
If flip-chip connection with solder bumps is used, then reliable electrical connection is achieved, but thickness and inductance increase
Solution Approach 1:
The invention extracts the solder bump connection step by using conductive bumps formed through copper plating instead. This eliminates the need for separate soldering process, reducing thickness while maintaining reliable electrical connection through the conductive bumps that are already integrated into the wiring layers.
Solution Approach 2:
The invention changes the material parameter from solder material to copper material for the conductive bumps. This parameter change allows the bumps to be formed through copper plating process during wiring layer formation, eliminating the need for additional soldering while achieving reliable electrical connection with reduced thickness.
3Device complexity
If wiring layers are stacked directly on resin sealed semiconductor element, then integration is achieved, but defects result in waste of semiconductor element
Solution Approach 1:
The invention segments the integrated structure into two separable components: chip sealed substrate and wiring substrate. This segmentation allows the chip sealed substrate to be prepared and inspected independently, so that wiring layer defects can be corrected without wasting the valuable resin sealed semiconductor element, while maintaining high integration level through subsequent connection.
Solution Approach 2:
The invention introduces conductive bumps as an intermediary connection element between the electrode terminals on the chip sealed substrate and the wiring layers on the wiring substrate. This intermediary allows for flexible connection and defect correction, enabling the chip sealed substrate to be reused or reconnected if wiring defects are found, thereby reducing waste.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the fabrication of thinner semiconductor element mounted wiring boards with reduced inductance, enhanced power supply characteristics, and increased yield by eliminating the need for solder connections and minimizing resin waste.
Implementation Method 1
a resin layer is formed so as to cover the metal plate and the semiconductor element
Implementation Method 2
connecting the electrode terminal to the conductive bump
Data Source
AI summary
A semiconductor element sealed substrate including a semiconductor element covered by an insulating layer is fabricated while a wiring substrate formed by stacking wiring layers is fabricated by a process different from the process of fabricating the semiconductor element sealed substrate. Next, the semiconductor element sealed substrate and the wiring substrate are stacked on each other in such a way that electrode terminals of the semiconductor element and corresponding conductive bumps on the outermost wiring layer face each other. The electrode terminals and the conductive bumps are thus connected to each other.