Multi-Layered Semiconductor Wiring for Current Density Management
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Solution Overview
Problem
Semiconductor devices with multiple elements connected in parallel face issues with maximum allowable current density, leading to electro-migration failures due to excessive electron collisions with wire material atoms, particularly when current density exceeds limits at wire leads.
Innovation Solution
The semiconductor device employs multi-layered wires with alternating and intersecting patterns, where each layer is connected via through-holes, allowing wider wires in higher layers to distribute current evenly and avoid partial concentration, thereby managing current density within acceptable limits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the wire length L is extended to connect more semiconductor elements in parallel, then the current capacity of the semiconductor device is enhanced, but the current density at the wire leads exceeds the maximum allowable current density, causing electro-migration failure
Solution Approach 1:
The wire is divided into multiple segments arranged in different layers (first layer wire, second layer wire, third layer wire). Each segment carries a portion of the total current, reducing the current density in any single wire segment while maintaining the overall current capacity of the device.
Solution Approach 2:
The wire structure transitions from a single-layer configuration to a multi-layer three-dimensional configuration. By stacking wires in multiple layers and connecting them through via holes, the patent creates additional current pathways in the vertical dimension, effectively distributing current across multiple spatial dimensions and reducing current density.
2Reliability
If the wire width is increased to reduce current density, then the current capacity per wire is improved, but the element area increases undesirably
Solution Approach 1:
Instead of increasing wire width in the horizontal plane, the patent utilizes the vertical dimension by stacking multiple wire layers. This allows the same current-carrying capacity to be achieved with smaller horizontal footprint, as the effective cross-sectional area for current flow is increased through the vertical stacking of multiple thinner wire segments.
Solution Approach 2:
The total current path is segmented into multiple parallel wire segments across different layers. Each segment can be kept narrow to minimize area, but collectively they provide sufficient current-carrying capacity through their combined cross-sectional area distributed across multiple layers.
3Power
If multi-layered wires are used to thicken the film thickness for large current flow, then the current capacity is improved, but partial concentration of current density occurs at intersections and connections
Solution Approach 1:
The patent implements alternating wide and narrow wire patterns in different layers. At intersection regions, wide wires in one layer alternate with narrow wires in adjacent layers, creating a checkerboard pattern. This local variation in wire width distributes the current density more evenly across the multi-layer structure, preventing concentration at specific intersection points while maintaining overall high current capacity.
Data Source
AI summary
A semiconductor device comprises a plurality of semiconductor elements; and a first wire and a second wire provided to connect the semiconductor elements in parallel. The first wire and the second wire include respective wires formed in multiple wiring layers. Each wiring layer includes the first wire and the second wire formed alternately and in parallel. The wires are formed as to intersect each other in adjacent wiring layers. The first wires are connected with each other through a via-connection at an intersection of the first wires and the second wires are connected with each other through a via-connection at an intersection of the second wires.