Semiconductor Wiring with Large Crystal Grains for Low Resistance
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Solution Overview
Problem
As semiconductor devices miniaturize, the resistance of wiring and vias increases due to the reduction in trench width, necessitating a renewal of wiring and via structures to achieve low-resistance fine-pitch wiring.
Innovation Solution
The semiconductor device incorporates a metal wiring and via structure with large crystal grains, where at least a part of each side surface cuts off metal crystal grains, and the content of fluorine is less than 1×10^19 atoms/cc, allowing for low-resistance performance even at miniaturized sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the trench width is reduced to achieve miniaturization of wirings and vias, then the device can be miniaturized, but the resistance of the wiring and via increases
Solution Approach 1:
The patent changes the physical parameters of the metal layer by controlling crystal grain size to be large (comparable to or larger than the trench width) and controlling fluorine content to be less than 1×10^19 atoms/cc. These parameter changes enable the metal to maintain low resistance even when the trench width is reduced for miniaturization, thus resolving the contradiction between device size reduction and resistance increase.
2Ease of manufacture
If conventional metal filling is used in miniaturized trenches, then the manufacturing process is simple, but the resistance becomes too high for acceptable performance
Solution Approach 1:
The patent modifies the material parameters by controlling crystal grain growth and fluorine content in the metal layer. This allows conventional metal filling processes to produce low-resistance structures in miniaturized trenches, maintaining ease of manufacture while achieving acceptable resistance levels.
Solution Approach 2:
The patent creates a composite structure where the metal layer has specific crystal grain characteristics (large grains) and controlled impurity content (low fluorine). This composite material approach enables the metal to exhibit superior electrical properties suitable for fine-pitch wiring while maintaining compatibility with existing manufacturing processes.
Data Source
AI summary
A first wiring is disposed over a semiconductor substrate. A first via is disposed over the first wiring. Further, the bottom surface of the first via is in contact with the first wiring. A first insulation layer is disposed over the semiconductor substrate, and is in contact with at least the top surface of the first wiring and the side surface of the first via. At least a part of each side surface of the first wiring and the first via cuts off each metal crystal grain.