Semiconductor Wiring Structure for Conductive Plug Short-Circuit Prevention
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Solution Overview
Problem
The challenge of short-circuiting conductive plugs in the peripheral region of semiconductor structures due to high-density integration, which causes damage to devices, is exacerbated by the increased height difference and reduced pitch between conductive plugs, leading to fabrication difficulties and reduced transmission efficiency.
Innovation Solution
A semiconductor structure design with a first wiring layer and conductive plugs that have a lower top surface than capacitor structures, along with a distribution of conductive plugs that reduces density and avoids short circuits, utilizing multi-layer wiring layers and conductive plugs to connect peripheral and array region devices efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If high-density integration is implemented to meet miniaturization requirements, then device integration density is improved, but conductive plugs in the peripheral region are prone to short-circuiting
Solution Approach 1:
The patent introduces a height dimension differentiation between array region and peripheral region, creating a stepped structure where capacitor structures extend higher than peripheral device structures. This vertical dimension separation allows conductive plugs in the peripheral region to be shorter and positioned at different heights, preventing short-circuits while maintaining high horizontal integration density.
Solution Approach 2:
The patent applies different structural characteristics to different regions: the array region has taller capacitor structures with larger charge storage capacity, while the peripheral region has shorter device structures with conductive plugs that don't extend as high. This local differentiation allows each region to be optimized for its specific function while avoiding the short-circuit problem in the peripheral region.
2Reliability
If conductive plugs are made higher to penetrate through thicker dielectric layers in the peripheral region, then electrical connection capability is improved, but the risk of short-circuiting increases
Solution Approach 1:
Instead of making all conductive plugs uniformly high, the patent uses the vertical dimension to create different plug heights in different regions. Peripheral region conductive plugs are shorter and terminate at appropriate levels, while array region capacitor structures extend higher. This dimensional approach maintains electrical connection capability without causing short-circuits.
Solution Approach 2:
The patent segments the conductive plug structures into different height levels - peripheral region plugs are segmented to be shorter and terminate before reaching the top of capacitor structures, while array region structures extend higher. This segmentation prevents harmful electrical interactions while maintaining necessary connections.
3Quantity of substance
If pitch between conductive plugs is reduced to increase integration density, then device density is improved, but fabrication precision requirements increase
Solution Approach 1:
The patent resolves the pitch and precision contradiction by moving to the vertical dimension. Instead of relying solely on horizontal spacing, the design uses height differentiation where peripheral conductive plugs terminate at lower levels than array region capacitor structures. This allows smaller horizontal pitch while maintaining adequate vertical separation, reducing the precision burden on fabrication processes.
Data Source
AI summary
Embodiments provide a semiconductor structure. The semiconductor structure includes: a substrate including a capacitor structure and a peripheral device structure; a first wiring layer including a first wiring sub-layer and a second wiring sub-layer, first conductive plugs being positioned between the first wiring layer and the peripheral device structures; a second wiring layer being positioned above the capacitor structures and the first wiring layer and second conductive plugs being positioned between the second wiring layer and the substrate, wherein a top surface of the first wiring layer is lower than the top surface of each of the capacitor structures, and heights of the first conductive plugs positioned between the first wiring sub-layer and the second wiring sub-layer are lower than heights of the first conductive plugs positioned between the first wiring sub-layer and the peripheral device structures.