Semiconductor Package Conductive Wiring via Soft-Lithography
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Solution Overview
Problem
The challenge in semiconductor packaging is the need for smaller, more integrated semiconductor chips, which requires a manufacturing process that eliminates the complexity and cost of photolithography, while ensuring reliable electrical connections and protection of the chip.
Innovation Solution
A semiconductor package is manufactured using a soft-lithography process to form conductive wiring and encapsulants without the need for photolithography, directly connecting the wiring to the chip pad and sealing member, and forming solder balls in a fan-out or fan-in structure to simplify the process and reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is used to form conductive wiring, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the photolithography step from the conventional semiconductor packaging process. Instead of using photolithography to form conductive wiring patterns, the invention directly forms conductive wiring on the semiconductor chip using alternative methods such as screen printing or direct deposition, thereby simplifying the manufacturing process while maintaining electrical connection reliability
Solution Approach 2:
The patent employs cost-effective, simple patterning techniques such as screen printing masks or direct paste deposition instead of expensive photolithography equipment and materials. These alternative methods use simpler, more economical materials and processes that achieve the same functional result of forming conductive pathways without requiring complex optical alignment systems
2Manufacturing precision
If photolithography process is used to form conductive wiring, then manufacturing precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent replaces expensive photolithography equipment and materials with inexpensive alternative methods such as screen printing, direct paste deposition, or simple stenciling. These methods use low-cost consumables and eliminate the need for expensive optical equipment, photore resists, and complex exposure/development processes while achieving adequate wiring formation precision
Solution Approach 2:
The invention removes the costly photolithography step from the manufacturing sequence and replaces it with direct, low-cost conductive material deposition or printing methods, thereby significantly reducing equipment investment, material costs, and process complexity
3Productivity
If semiconductor chips are made smaller for higher integration, then productivity is improved, but reliability of electrical connections deteriorates
Solution Approach 1:
The patent applies localized conductive wiring formation techniques that concentrate electrical connection materials precisely at required pad locations on the chip surface. By using direct deposition or screen printing methods, the invention ensures adequate material volume and contact area at each connection point, maintaining reliability even as chip size decreases and integration density increases
Data Source
AI summary
In one embodiment, a semiconductor package may include a semiconductor chip having a chip pad formed on a first surface thereof, a sealing member for sealing the semiconductor chip and exposing the first surface of the semiconductor chip, a conductive wiring overlying a part of the first surface of the semiconductor chip and directly contacting a part of an upper surface of the sealing member. The conductive wiring further contacts the pad. The semiconductor package may also include an encapsulant covering the conductive wiring and having openings for exposing parts of the conductive wiring.