Semiconductor Device Wiring Substrate Noise Reduction
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Solution Overview
Problem
Current semiconductor devices face challenges in enhancing the transmission speed and stability of high-speed signal processing, particularly in reducing noise interference and power supply stability, which affects the performance and size of the devices.
Innovation Solution
The semiconductor device incorporates a wiring substrate with input signal wires of smaller cross-sectional area than output signal wires, with conductor patterns supplied with a reference potential interposed between them, and strategically disposed to reduce electromagnetic noise and stabilize power supply to the core circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the wire cross-sectional area of input signal wires is increased to reduce noise interference, then the noise resistance is improved, but the device size increases
Solution Approach 1:
The patent applies different wire cross-sectional areas to different signal types: input signal wires have a smaller cross-sectional area while output signal wires have a larger cross-sectional area. This local differentiation optimizes noise resistance where needed (input wires) without unnecessarily increasing the overall device size, as each wire's dimensions are tailored to its specific functional requirements.
2Object-affected harmful factors
If conductor patterns supplied with reference potential are added between input and output signal wires to reduce electromagnetic noise, then the noise resistance is improved, but the wiring complexity increases
Solution Approach 1:
The patent introduces conductor patterns supplied with reference potential as intermediary elements positioned between the input signal wires and output signal wires. These conductor patterns act as shielding intermediaries that reduce electromagnetic noise coupling between the signal wires, improving noise resistance while maintaining a manageable wiring structure through systematic placement.
3Productivity
If the transmission speed of input/output signals is increased to improve data processing performance, then the productivity is improved, but the signal integrity deteriorates due to noise
Solution Approach 1:
The patent optimizes the cross-sectional area parameters of the signal wires to balance transmission speed and signal integrity. By carefully selecting the wire dimensions, the patent achieves high-speed signal transmission while maintaining sufficient noise resistance, allowing fast data processing without compromising signal quality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the performance by reducing noise interference and enhancing power supply stability, allowing for higher transmission speeds and more efficient data processing while maintaining a compact device size.
Implementation Method 1
each of the plurality of input signal wires is interposed between the plurality of conductor patterns supplied with the reference potential
Implementation Method 2
Between the plurality of output signal wires and the plurality of input signal wires, the respective conductor patterns supplied with the reference potential are disposed
Data Source
AI summary
A semiconductor device includes a semiconductor chip including a first circuit and a wiring substrate over which the semiconductor chip is mounted. The wiring substrate includes input signal wires transmitting an input signal to the semiconductor chip, output signal wires transmitting an output signal from the semiconductor chip, and first conductor planes supplied with a reference potential. When a wire cross-sectional area is defined as the cross-sectional area of each wire in a direction orthogonal to a direction in which the wire extends, the wire cross-sectional area of each input signal wire is smaller than the wire cross-sectional area of each output signal wire. In the thickness direction of the wiring substrate, each input signal wire is interposed between second conductor planes and third conductor planes each supplied with the reference potential. Between the output signal wires and the input signal wires, the third conductor planes are disposed.