Sense Amplifier Array for Nonvolatile Memory Noise Reduction
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Solution Overview
Problem
Current non-volatile memory technologies face challenges in achieving high capacity and performance due to noise and interference among closely packed memory cells, which limit sensing accuracy and storage capacity.
Innovation Solution
The implementation of a sensing circuit that includes a precharge circuit, an intermediate circuit, a comparator circuit, and a data latch, allowing for concurrent precharging and independent data transfer to a data bus, thereby reducing noise and improving sensing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are closely packed to increase storage capacity, then storage density is improved, but noise and interference among cells increase, degrading sensing accuracy
Solution Approach 1:
The sensing circuit is divided into multiple independent sense amplifiers, each dedicated to sensing a specific memory cell or group of cells. This segmentation isolates the sensing operations, preventing noise and interference from propagating between adjacent cells, thereby maintaining sensing accuracy while enabling higher storage density through closer cell packing.
Solution Approach 2:
Dedicated bit lines and word lines are introduced as intermediary elements between memory cells and sense amplifiers. These intermediaries provide isolated signal pathways for each cell, preventing direct electrical interference between closely packed cells while allowing high-density arrangement. The intermediaries act as buffers that maintain signal integrity despite increased cell density.
2Device complexity
If conventional sensing circuits are used, then circuit simplicity is maintained, but sensing speed is limited due to sequential operations
Solution Approach 1:
The sense amplifiers are precharged to a predetermined voltage level before the actual sensing operation begins. This preliminary action prepares the amplifiers in advance, allowing them to immediately respond to and amplify the small current signals from memory cells as soon as the sensing operation starts, thereby reducing the overall sensing time without adding complex circuitry.
Solution Approach 2:
Multiple sense amplifiers operate simultaneously and continuously during the sensing process, with each amplifier dedicated to a specific cell. This parallel operation eliminates the sequential bottlenecks of conventional circuits, maintaining relative circuit simplicity while achieving significantly higher sensing speeds through concurrent multi-cell sensing operations.
3Measurement precision
If precharging is performed before sensing, then sensing accuracy is improved, but operation time increases due to sequential precharge-sense sequence
Solution Approach 1:
The sense amplifiers are precharged to the required voltage level in advance, during which time the memory cell data is being prepared and other circuit elements are being configured. This preliminary precharging action overlaps with other preparation operations, so the actual sensing operation can begin immediately without waiting for sequential completion of prior steps, thereby maintaining accuracy while reducing total operation time.
Solution Approach 2:
The precharging of sense amplifiers is performed continuously and simultaneously with other sensing preparation activities across multiple cells. Rather than sequentially precharging one amplifier at a time, all sense amplifiers are precharged in parallel during the same time window, eliminating idle time and ensuring that the sensing operation can commence immediately across all cells, thus maintaining accuracy without extending operation time.
Data Source
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AI summary
Sensing circuits for sensing a conduction current of a memory cell among a group of non-volatile memory cells being sensed in parallel and providing the result thereof to a data bus are presented. A precharge circuit is coupled to a node for charging the node to an initial voltage. An intermediate circuit is also coupled to the node and connectable to the memory cell, whereby current from the precharge circuit can be supplied to the memory cell. The circuit also includes a comparator circuit to perform a determination the conduction current by a rate of discharge at the node; a data latch coupled to the comparator circuit to hold the result of said determination; and a transfer gate coupled to the data latch to supply a result latched therein to the data bus independently of the node. This arrangement improves sensing performance and can help to eliminate noise on the analog sensing path during sensing and reduce switching current.