Sense Amplifier Biased Read Logic Complementary Resistive Memory

Solution Overview

Problem

Complementary Magnetic Tunneling Junction (MTJ) based memory bit-cells suffer from retention errors due to uncertainty in read mode, leading to conflicting sensing modes when one MTJ flips, causing errors in storing '0' and '1' values, which existing solutions attempt to address with complex reading logic and increased latency.

Innovation Solution

The implementation of a Sense Amplifier circuit with biased read logic and additional status bits to conditionally invert data in the memory array, forcing the majority bit value to a predefined state, thereby reducing retention failures by ensuring a greater than 50% correct read rate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a second read mode is employed to identify conflicts by reading two MTJs separately, then reading accuracy is improved, but reading logic complexity increases and reading latency increases

Engineering Contradiction:

Improvereading accuracyVSAvoidreading logic complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by performing a first read operation to sense both MTJs simultaneously before any conflict detection or resolution is needed. The sense amplifier is configured to produce a deterministic output based on the initial state, and only then is a second read operation performed if needed. This reverses the conventional approach of first reading both bits and then detecting conflicts, thereby reducing the complexity and latency of the reading logic while maintaining reliability.

Inventive Principle:

Principle #10Preliminary action

2Reliability

If a second read mode is employed to identify conflicts by reading two MTJs separately, then reading accuracy is improved, but reading latency increases

Engineering Contradiction:

Improvereading accuracyVSAvoidreading latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by performing a first read operation to sense both MTJs simultaneously before any conflict detection or resolution is needed. The sense amplifier is configured to produce a deterministic output based on the initial state, and only then is a second read operation performed if needed. This reverses the conventional approach of first reading both bits and then detecting conflicts, thereby reducing the complexity and latency of the reading logic while maintaining reliability.

Inventive Principle:

Principle #10Preliminary action

3Measurement precision

If complementary MTJ bit-cells are used to provide larger sensing margin, then sensing capability is improved, but retention error uncertainty increases

Engineering Contradiction:

Improvesensing marginVSAvoidretention error uncertainty

Core Design Contradiction:

Measurement precisionVSReliability

Solution Approach 1:

The patent applies feedback by using the output of the first read operation to determine whether a second read operation is necessary. The sense amplifier's deterministic output is fed back to the reading logic, which then decides whether to perform the additional second read operation for conflict resolution. This feedback mechanism allows the system to maintain the sensing margin benefits of complementary MTJ bit-cells while reducing retention error uncertainty through selective redundant reading only when needed.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS9830988B2Apparatus to reduce retention failure in complementary resistive memory

Publication Date: 2017.11.28 TAHOE RES LTD

AI summary

Described is an apparatus which comprises: a complementary resistive memory bit-cell; and a sense amplifier coupled to the complementary resistive memory bit-cell, wherein the sense amplifier includes: a first output node; and a first transistor which is operable to cause a deterministic output on the first output node.