Sense Amplifier Using Unused Bit Lines for Reference
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Solution Overview
Problem
Existing non-volatile memory systems face challenges in providing reliable reference values due to parasitic capacitance changes and leakage currents, leading to incorrect data readings and the need for separate reference cell circuits.
Innovation Solution
The implementation of a sensing circuit that uses bit lines from an unused memory array to provide reference values, eliminating the need for separate reference cell circuits and incorporating a self-test mechanism to identify bit lines with excessive leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate reference cell circuits are used to provide reference values, then reference comparison can be performed, but parasitic capacitance changes and leakage currents cause incorrect data readings
Solution Approach 1:
The patent merges the reference cell functionality into the memory array structure itself by using bit lines from the same array. During read operations, one memory cell is selected for reading while another cell on the same bit line serves as the reference cell. This eliminates separate reference cell circuits and ensures both the memory cell and reference cell experience identical parasitic capacitance conditions, thereby compensating for parasitic effects and leakage currents.
Solution Approach 2:
The patent introduces a differential sensing approach where the difference between the memory cell current and reference cell current is measured. This differential measurement acts as an intermediary that cancels out common-mode errors from parasitic capacitance and leakage currents, improving reading reliability without requiring separate reference circuits.
2Reliability
If separate reference cell circuits are used, then reference values can be provided, but device complexity increases
Solution Approach 1:
The patent makes the memory array bits serve dual purposes: storing data and providing reference values. Each bit line can function as both a data transmission line and a reference line, depending on which cells are selected. This multi-functionality eliminates the need for dedicated reference cell circuits, reducing device complexity while maintaining reference value accuracy.
Solution Approach 2:
The patent combines the data storage function and reference function into the same physical structure (memory array and bit lines). By selecting different cells on the same bit line for data and reference purposes, the system eliminates separate reference cell circuits, thereby reducing overall device complexity while maintaining accurate reference comparisons.
3Device complexity
If bit lines change with each read operation to provide reference values, then separate reference cell circuits are eliminated, but power consumption increases due to dynamic switching
Solution Approach 1:
The patent implements periodic pre-charging of bit lines before read operations. By pre-charging the bit lines to a known voltage state before selecting memory cells, the system reduces the energy required during the actual read operation. This periodic preparation minimizes dynamic power consumption while still allowing flexible bit line assignment for reference values.
Solution Approach 2:
The patent performs preliminary pre-charging of bit lines before the actual read operation occurs. This preliminary action prepares the bit lines in advance, reducing the energy required during the critical read phase. By pre-establishing the electrical state of bit lines, the system reduces dynamic power consumption while maintaining the ability to use bit lines for reference comparisons.
Data Source
AI summary
An improved sensing circuit is disclosed that utilizes a bit line in an unused memory array to provide reference values to compare against selected cells in another memory array. A circuit that can perform a self-test for identifying bit lines with leakage currents about an acceptable threshold also is disclosed.