Sense Amplifier Pairing for Faster MLC Verify Operations
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Solution Overview
Problem
The speed of sensing operations in non-volatile memory devices, particularly in multi-level cell (MLC) formats, is limited by the sequential nature of verify operations, where pre-charging of sense nodes must wait for previous logical operations to complete, leading to inefficiencies in programming and verification processes.
Innovation Solution
Implementing a technique where sense amplifiers are connected in pairs through an Odd-Even connection circuit, allowing logical operations to be performed on one tier's local data bus while the sense node of the other tier is pre-charged for subsequent sensing operations, thereby enabling concurrent pre-charging and logical operation phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If sequential verify operations are used in MLC sensing, then logical operations can be performed accurately, but pre-charging of sense nodes must wait for previous logical operations to complete, reducing sensing speed
Solution Approach 1:
The sense amplifier system is divided into multiple independent tiers, each capable of performing sensing operations autonomously. This segmentation allows different tiers to operate in parallel, with one tier performing logical operations while another tier performs pre-charging, thereby resolving the sequential bottleneck without compromising sensing accuracy
Solution Approach 2:
The pre-charging operation is performed in advance during the logical operation phase of a previous tier. By preparing the sense node beforehand, the system eliminates waiting time and enables immediate sensing when needed, thus improving speed while maintaining measurement precision
2Measurement precision
If pre-charging waits for logical operations to complete, then sensing accuracy is maintained, but programming and verification time increases
Solution Approach 1:
The system maintains continuous useful action by overlapping pre-charging operations with logical operations across different tiers. While one tier performs logical operations, another tier simultaneously performs pre-charging, ensuring that no time is wasted and the overall programming and verification process is accelerated without sacrificing verify accuracy
3Device complexity
If sequential sensing operations are used, then circuit complexity is reduced, but productivity of memory operations decreases
Solution Approach 1:
The system transitions from sequential (one-dimensional) operation to parallel (multi-dimensional) operation by introducing multiple tiers that can operate simultaneously. This dimensional change enables concurrent pre-charging and logical operations, significantly improving memory operation throughput while adding only moderate circuit complexity through the Odd-Even connection circuit
Data Source
AI summary
A local data bus of a sense amplifier associated with one bit line is used to perform logical operations for a sensing operation performed by another sense amplifier associated with a different bit line. Each sense amplifier circuit includes a sensing node that is pre-charged, then discharged through a selected memory cell and a local data bus with a number of data latches connected. Target program data can be stored in the latches and combined in logical combinations with the sensed value of the memory cell to determine whether it has verified. By including a transfer circuit between the local data buses of a pair of sense amplifiers, the logical operations of a first sense amplifier can be performed using the local data bus of the paired sense amplifier, freeing the first sense amplifier's sense node to be concurrently pre-charged for a subsequent sensing operation, thereby improving performance.