Voltage-Mode Sense Amplifier Offset Nulling Without Slew-Rate Loss
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Solution Overview
Problem
High-speed voltage-mode sense amplifiers face challenges in offset nulling, as existing methods introduce parasitic capacitance that slows down slew rates, making them unsuitable for high-data-rate applications.
Innovation Solution
A voltage-mode sense amplifier design where one evaluation node is charged to the power supply voltage during the reset phase and the other to the power supply voltage minus an ohmic voltage drop, using a current source and resistors to minimize capacitive loading, allowing for offset nulling without hampering the slew rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional offset calibration techniques (incremental transistor switching or additional differential pair) are used, then the offset voltage is nulled, but parasitic capacitance is introduced that slows down the slew rate
Solution Approach 1:
A current source is introduced as an intermediary element to create an artificial voltage offset that counteracts the inherent circuit offset. This current source flows through a resistor to generate a compensating voltage at one of the evaluation nodes, allowing offset nulling without requiring additional transistors or differential pairs that would introduce parasitic capacitance
Solution Approach 2:
The invention changes the operating parameters by introducing a controllable current source that can be adjusted during calibration. By varying the current through the resistor, the voltage offset can be precisely tuned to match and cancel the inherent circuit offset, achieving nulling without structural modifications that would degrade speed
2Measurement precision
If additional transistors are switched on to boost the weaker transistor in the differential pair, then the offset is reduced, but the parasitic capacitance at the drain terminals increases
Solution Approach 1:
The invention extracts the offset compensation function from the differential pair transistors themselves and relocates it to a separate current source and resistor combination. This separation allows the differential pair to operate with minimal parasitic capacitance while the offset nulling function is performed by the external current source circuitry
Solution Approach 2:
A resistor is introduced as an intermediary element between the current source and the evaluation node. This resistor converts the current from the current source into a voltage that can directly compensate for the offset at the evaluation node, avoiding the need to modify the differential pair transistors
3Measurement precision
If an additional differential pair is coupled in parallel with the original differential pair, then offset nulling is achieved through two-port differential adjustment, but the parasitic capacitance at the evaluation nodes increases
Solution Approach 1:
Instead of using an additional differential pair, the invention uses a current source and resistor as intermediary elements to achieve offset nulling. This approach directly injects a compensating current at one evaluation node without requiring the complex interconnections and additional transistors of a second differential pair
Solution Approach 2:
The invention changes the calibration approach from structural modification (adding a second differential pair) to parameter adjustment (modifying the current through a resistor). This allows offset nulling to be achieved by simply adjusting the current source parameter without adding parasitic capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively nulls the offset without significant capacitive loading, enhancing high-speed operation by maintaining the slew rate of the evaluation nodes, thus improving the performance of voltage-mode sense amplifiers in high-data-rate applications.
Implementation Method 1
a remaining evaluation node from the pair of evaluation nodes is charged to the power supply voltage minus a ohmic voltage drop produced by a current sourced through a resistor
Data Source
AI summary
A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.