Memory Device Sense Amplifier Timing for Accurate DRAM Reading
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Solution Overview
Problem
Existing dynamic random access memory (DRAM) technologies face challenges in efficiently amplifying and determining stored data due to variations in transistor resistance and parasitic capacitance, leading to inaccuracies in data reading.
Innovation Solution
A memory device structure incorporating a capacitor, transistors, and inverter circuits with specific voltage applications and timing controls to stabilize and amplify bit line potentials, utilizing bias circuits and sense amplifier control circuits to manage transistor resistance and parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sense amplifier circuits are used to amplify bit line potentials, then data reading function is achieved, but variations in transistor resistance and parasitic capacitance cause amplification inaccuracies
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit lines to a predetermined potential before the read operation. The bit line potential is set to a specific voltage level in advance, and the sense amplifier is pre-configured with appropriate gate voltages. This preliminary preparation ensures that when the read operation commences, the amplification process starts from a known, stable state, eliminating errors caused by transient variations in transistor resistance and parasitic capacitance.
Solution Approach 2:
The patent utilizes parameter changes by dynamically adjusting the gate voltages of the sense amplifier transistors during the read operation. Specifically, the gate potentials of the pull-up and pull-down transistors are changed at different timings to compensate for variations in transistor characteristics. By changing these voltage parameters adaptively, the sense amplifier maintains high amplification accuracy despite variations in transistor resistance and parasitic capacitance.
2Reliability
If multiple voltages are applied to sense amplifier nodes, then transistor resistance and parasitic capacitance are controlled, but voltage application timing control complexity increases
Solution Approach 1:
The patent applies self-service by designing the sense amplifier control circuit to automatically generate the required gate voltages based on the read operation timing. The control circuit monitors the read operation state and autonomously applies the appropriate voltages to the sense amplifier nodes without requiring external intervention or complex timing control mechanisms. This self-managing approach simplifies the overall control architecture while maintaining precise voltage application timing.
3Measurement precision
If bit line potential is stabilized before reading, then data determination accuracy is improved, but read operation time increases
Solution Approach 1:
The patent applies continuity of useful action by maintaining the bit line potential at the predetermined level continuously throughout the read operation. Instead of periodically adjusting or re-charging the bit lines, the potential is kept stable from the start of the read operation until completion. This continuous stabilization ensures that the amplification process occurs in a consistently optimal environment, achieving high data determination accuracy without requiring multiple stabilization cycles that would increase read time.
Data Source
AI summary
A first inverter circuit including second and third transistors coupled at a third node and a second inverter circuit including fourth and fifth transistors coupled at a fourth node are coupled between first and second nodes. An eighth transistor is coupled between a gate of the third transistor and the third node. A ninth transistor is coupled between a gate of the fifth transistor and the fourth node. A state in which first and second voltages are applied to the first and second nodes is formed at a first time. A third voltage is applied to the first node at a second time. A fourth voltage is applied to the second node at a third time. The second voltage is applied to the second node at a fourth time. The first voltage is applied to the first node at a fifth time.