Integrated Sensing and Computing Chip Package
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization and increased complexity of semiconductor chips in optoelectronic products, such as digital cameras and solar cells, lead to difficulties in packaging and reduced yield due to the need for individual packaging of light sensing and computing elements, which complicates the formation of complete semiconductor devices.
Innovation Solution
A chip package and manufacturing method that integrates a sensing chip and a computing chip within the same package, utilizing a protective layer annularly surrounding both chips, along with a conductive layer and a transparent substrate, to enhance electrical insulation and reduce leakage current, while allowing for efficient light transmission and protection of the sensing element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sensing chip and computing chip are packaged separately and connected by external conductive structures, then each chip can be individually packaged, but the packaging difficulty increases and yield decreases
Solution Approach 1:
The patent merges the sensing chip and computing chip into a single integrated package structure. The sensing chip is positioned on the first surface of the substrate while the computing chip is positioned on the second surface, with conductive layers providing electrical connections between them. This integration eliminates the need for separate packaging and external conductive structures, thereby simplifying the packaging process and improving manufacturing ease while reducing overall device complexity.
2Reliability
If protective layer is formed to surround sensing chip and computing chip, then leakage current decreases and protective effect is enhanced, but manufacturing process becomes more complex
Solution Approach 1:
The protective layer serves multiple functions simultaneously: it provides electrical insulation to reduce leakage current, offers mechanical protection to both chips, and acts as a structural element in the package. By forming a continuous protective layer that surrounds both the sensing chip and computing chip, the patent achieves enhanced reliability through leakage current reduction while avoiding the need for separate protective structures for each chip, thereby simplifying the manufacturing process.
3Adaptability or versatility
If chip size is miniaturized and function is made more complex, then product functionality improves, but packaging difficulty increases and yield decreases
Solution Approach 1:
The patent utilizes the third dimension by positioning the sensing chip on the first surface of the substrate and the computing chip on the second surface, effectively stacking components vertically. This three-dimensional arrangement allows miniaturization and increased functionality within a compact package volume, while the integrated package structure and conductive layers simplify the manufacturing process compared to traditional two-dimensional separate packaging approaches.
Data Source
AI summary
A chip package includes a sensing chip, a computing chip, and a protective layer annularly surrounding the sensing chip and the computing chip. The sensing chip has a first conductive pad, a sensing element, a first surface and a second surface opposite to each other. And the sensing element is disposed on the first surface. The computing chip has a second conductive pad and a computing element. The protective layer is formed by lamination and at least exposes the sensing element. The chip package further includes a conductive layer underneath the second surface of the sensing chip and extending to be in contact with the first conductive pad and the second conductive pad.