Sensor Chip Stack With Exposed Terminals And Molded Stability
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Solution Overview
Problem
Existing semiconductor sensor devices face challenges in efficiently integrating large detection area capabilities and manufacturing methods for such devices, particularly in arranging and connecting sensor chips with control and readout circuits effectively.
Innovation Solution
A sensor chip stack design where sensor substrates with integrated sensors are connected via electric terminals and pad connections, with through-chip metallization and sidewall metallization providing electrical interconnections, allowing for separate integration of detector and control circuits, and using a molding material that does not cover the electric terminals for mechanical stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chips are stacked and bonded in a flip-chip manner to form a chip-on-wafer structure, then electrical connections between chips are achieved, but the device complexity increases due to the need for through electrodes and mold layers
Solution Approach 1:
The patent segments the sensor device into separate functional modules: a sensor chip for light detection and a control chip for signal processing. These chips are stacked and bonded in a flip-chip manner, with through electrodes providing electrical connections between the layers. This segmentation allows each chip to be optimized for its specific function while maintaining reliable electrical interconnections through the stacked architecture.
2Stability of the object's composition
If a mold layer is formed to cover the chips and provide rigidity, then mechanical stability is improved, but the electric terminals are covered and not accessible
Solution Approach 1:
The patent extracts the electric terminals from the coverage of the mold layer by forming openings in the mold layer at the locations of the terminals. This allows the mold layer to provide rigidity and mechanical protection to the stacked chips while maintaining accessibility of the electric terminals for external electrical connections. The openings are precisely positioned to expose only the terminal regions without compromising the structural integrity provided by the mold layer.
3Length of stationary object
If the substrate of the further chip is thinned from its rear surface, then the device profile is reduced, but the manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary thinning of the substrate from the rear surface before completing the stacking and bonding process. This preliminary action allows for controlled reduction of substrate thickness to achieve a compact device profile while maintaining sufficient mechanical strength. The thinning is performed in advance to facilitate subsequent processing steps and to ensure that the final stacked structure meets the desired dimensional specifications.
4Adaptability or versatility
If detector part and control circuits are integrated in separate chips, then functional integration is improved, but the device complexity increases due to multiple chips and interconnections
Solution Approach 1:
The patent merges the detector part and control circuits into a single integrated stacked structure. The sensor chip containing photodiodes or active pixels is bonded to a control chip containing readout and processing circuits through flip-chip bonding. Through electrodes and pad connections establish electrical interconnections between the layers, creating a compact three-dimensional integrated device that combines multiple functions in a unified structure.
Data Source
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AI summary
The sensor chip stack comprises a sensor substrate (1) of a semiconductor material including a sensor, a chip (10) fastened to the sensor substrate, the chip including an integrated circuit (11), electric interconnections (4) between the sensor substrate and the chip, electric terminals (19) of the chip, the chip being arranged between the electric terminals and the sensor substrate, and a molding material (13) arranged adjacent to the chip, the electric terminals of the chip being free from the molding material.