Photoelectric Sensor Transistor Layout for Low Capacitance Hardness

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Solution Overview

Problem

Current top-gate transistors used in photoelectric sensing devices have a relatively small gate-drain capacitance but poor radiation hardness compared to bottom-gate transistors.

Innovation Solution

The transistor device includes a substrate with a gate, gate dielectric layer, semiconductor layer, and source and drain. The semiconductor layer has a first region overlapping with the gate and a second region with a dopant, extending to the edge of the semiconductor layer. The source and drain are electrically connected to the second region and do not overlap with the gate, reducing parasitic capacitance. Additionally, the gate dielectric layer in contact with the semiconductor layer includes a silicon nitride-based material for improved radiation hardness.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a top-gate transistor configuration is used, then the gate-drain capacitance is reduced, but the radiation hardness deteriorates

Engineering Contradiction:

Improvegate-drain capacitanceVSAvoidradiation hardness

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The transistor structure is divided into distinct regions: a first semiconductor region directly over the gate for low capacitance, and a second semiconductor region extending to the edge for radiation hardness. This segmentation allows each region to optimize for its specific function while working together as a unified device.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different regions of the semiconductor layer are given different properties: the first region is positioned to minimize capacitance with the gate, while the second region is positioned to maximize radiation hardness. This local differentiation resolves the contradiction by allowing each area to excel at its specific requirement.

Inventive Principle:

Principle #3Local quality

2Area of stationary object

If the semiconductor layer extends under the gate, then the gate-drain capacitance increases, but the device area is reduced

Engineering Contradiction:

Improvedevice areaVSAvoidgate-drain capacitance

Core Design Contradiction:

Area of stationary objectVSReliability

Solution Approach 1:

The semiconductor layer is configured to extend in the lateral dimension to the edge of the gate, rather than extending vertically underneath. This dimensional approach maintains compact device area while preventing the capacitance-increasing overlap between gate and drain regions.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250133844A1Transistor device and photoelectric sensing device

Publication Date: 2025.04.24 INNOCARE OPTOELECTRONICS CORP

AI summary

A transistor device includes a substrate and a transistor. The transistor is disposed on the substrate and includes a gate, a gate dielectric layer, a semiconductor layer, a source and a drain. The gate dielectric layer is disposed on the gate. The semiconductor layer is disposed on the gate dielectric layer, and includes a first region and a second region. The first region at least partially overlaps with the gate in a normal direction of the substrate, the second region extends from the first region to an edge of the semiconductor layer, and the second region further includes a dopant compared to the first region. The source and the drain are disposed on the semiconductor layer, and are electrically connected to the second region of the semiconductor layer. At least one of the source and the drain does not overlap with the gate in the normal direction of the substrate.